intel/sch: Merge northbridge and southbridge in src/soc

Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

1 files changed, 72 insertions, 0 deletions

diff --git a/src/soc/intel/sch/acpi.c b/src/soc/intel/sch/acpi.c
new file mode 100644
index 0000000000..2c941d868e
--- /dev/null
+++ b/src/soc/intel/sch/acpi.c
@@ -0,0 +1,72 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cbmem.h>
+#include <arch/acpigen.h>
+#include <cpu/cpu.h>
+#include "sch.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+	device_t dev;
+	u32 pciexbar = 0;
+	u32 pciexbar_reg;
+	int max_buses;
+
+	dev = dev_find_device(0x8086, 0x27a0, 0);
+	if (!dev)
+		return current;
+
+	pciexbar_reg = pci_read_config32(dev, 0x48);
+
+	/* MMCFG not supported or not enabled. */
+	if (!(pciexbar_reg & (1 << 0)))
+		return current;
+
+	switch ((pciexbar_reg >> 1) & 3) {
+	case 0: /* 256MB */
+		pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+					   (1 << 28));
+		max_buses = 256;
+		break;
+	case 1: /* 128M */
+		pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+					   (1 << 28) | (1 << 27));
+		max_buses = 128;
+		break;
+	case 2: /* 64M */
+		pciexbar = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) |
+					   (1 << 28) | (1 << 27) | (1 << 26));
+		max_buses = 64;
+		break;
+	default: /* RSVD */
+		return current;
+	}
+
+	if (!pciexbar)
+		return current;
+
+	current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+					     pciexbar, 0x0, 0x0, max_buses - 1);
+	return current;
+}