diff options
| author | Martin Roth <gaumless@gmail.com> | 2017-10-15 14:20:28 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:23:30 +0000 |
| commit | 0026a53562595cafb466e4ff836c50a7817d5297 (patch) | |
| tree | 4d5f4062df24cdaa0109e9bddac81c587ea36d0e /src/soc/intel/sch/Kconfig | |
| parent | 732fb2ab5363968a12b2270319189c2a2a536a36 (diff) | |
Intel sch board & chip: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
soc/intel/sch
Mainboards:
mainboard/iwave/iWRainbowG6
Change-Id: Ida0570988a23fd0d13c6fcbe54f94ab0668c9eae
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/soc/intel/sch/Kconfig')
| -rw-r--r-- | src/soc/intel/sch/Kconfig | 59 |
1 files changed, 0 insertions, 59 deletions
diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig deleted file mode 100644 index 2456df79ca..0000000000 --- a/src/soc/intel/sch/Kconfig +++ /dev/null @@ -1,59 +0,0 @@ -# -# This file is part of the coreboot project. -# -# Copyright (C) 2007-2010 coresystems GmbH -# -# This program is free software; you can redistribute it and/or modify -# it under the terms of the GNU General Public License as published by -# the Free Software Foundation; version 2 of the License. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# - -config SOC_INTEL_SCH - bool - select LATE_CBMEM_INIT - select INTEL_GMA_ACPI - select SOUTHBRIDGE_INTEL_COMMON - select HAVE_USBDEBUG - select HAVE_HARD_RESET - select HAVE_SMI_HANDLER - -if SOC_INTEL_SCH - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/sch/bootblock.c" - -config VGA_BIOS_ID - string - default "8086,8108" - -config EHCI_BAR - hex - default 0xfef00000 - -config HAVE_CMC - bool "Add a CMC state machine binary" - help - Select this option to add a CMC state machine binary to - the resulting coreboot image. - - Note: Without this binary coreboot will not work - -config CMC_FILE - string "Intel CMC path and filename" - depends on HAVE_CMC - default "cmc.bin" - help - The path and filename of the file to use as CMC state machine - binary. - -config HPET_MIN_TICKS - hex - default 0x80 - -endif |