intel/sch: Merge northbridge and southbridge in src/soc

Change-Id: I6ea9b9d2353c0d767c837e6d629b45f23b306f6e
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/14599
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>

1 files changed, 56 insertions, 0 deletions

diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig
new file mode 100644
index 0000000000..6bbb168782
--- /dev/null
+++ b/src/soc/intel/sch/Kconfig
@@ -0,0 +1,56 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2010 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+
+config SOC_INTEL_SCH
+	bool
+	select MMCONF_SUPPORT
+	select LATE_CBMEM_INIT
+	select INTEL_GMA_ACPI
+	select SOUTHBRIDGE_INTEL_COMMON
+	select HAVE_USBDEBUG
+	select HAVE_HARD_RESET
+	select HAVE_SMI_HANDLER
+
+if SOC_INTEL_SCH
+
+config VGA_BIOS_ID
+	string
+	default "8086,8108"
+
+config EHCI_BAR
+	hex
+	default 0xfef00000
+
+config HAVE_CMC
+	bool "Add a CMC state machine binary"
+	help
+	  Select this option to add a CMC state machine binary to
+	  the resulting coreboot image.
+
+	  Note: Without this binary coreboot will not work
+
+config CMC_FILE
+	string "Intel CMC path and filename"
+	depends on HAVE_CMC
+	default "cmc.bin"
+	help
+	  The path and filename of the file to use as CMC state machine
+	  binary.
+
+config HPET_MIN_TICKS
+	hex
+	default 0x80
+
+endif