soc/intel/quark: Add FSP 2.0 romstage support

Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build.  Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.

TEST=Build and run on Galileo Gen2

Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

8 files changed, 281 insertions, 4 deletions

diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index 4924b86372..3950d43f3f 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -135,6 +135,13 @@ config DCACHE_RAM_SIZE
 	default 0x8000 if PLATFORM_USES_FSP1_1
 	default 0x40000
 
+config DISPLAY_ESRAM_LAYOUT
+	bool "Display ESRAM layout"
+	default n
+	depends on PLATFORM_USES_FSP2_0
+	help
+	  Select this option to display coreboot's use of ESRAM.
+
 #####
 # Flash layout
 #     Specify the size of the coreboot file system in the read-only
@@ -196,8 +203,8 @@ config FSP_LOC
 
 config FSP_ESRAM_LOC
 	hex
-	default 0x80000000
-	depends on PLATFORM_USES_FSP1_1
+	default 0x80000000 if PLATFORM_USES_FSP1_1
+	default 0x80040000
 	help
 	  The location in ESRAM where a copy of the FSP binary is placed.
 
@@ -208,6 +215,16 @@ config RELOCATE_FSP_INTO_DRAM
 	help
 	  Relocate the FSP binary into DRAM before the call to SiliconInit.
 
+config FSP_M_FILE
+	string
+	depends on PLATFORM_USES_FSP2_0
+	default "3rdparty/blobs/soc/intel/quark/FSP_M.fd"
+
+config FSP_S_FILE
+	string
+	depends on PLATFORM_USES_FSP2_0
+	default "3rdparty/blobs/soc/intel/quark/FSP_S.fd"
+
 #####
 # RMU binary
 #     The following options control the Quark chipset microcode file
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index a6454d9a1c..bd297ed8d7 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -30,6 +30,14 @@ romstage-y += memmap.c
 romstage-y += reg_access.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+
+postcar-y += fsp2_0.c
+postcar-y += i2c.c
+postcar-y += memmap.c
+postcar-y += reg_access.c
+postcar-y += tsc_freq.c
+postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
@@ -54,6 +62,9 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
 # Chipset microcode path
 CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
 
+# Since FSP-M runs in CAR we need to relocate it to a specific address
+$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC)
+
 # Add the FSP binary to the CBFS image
 cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
 fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))
diff --git a/src/soc/intel/quark/fsp2_0.c b/src/soc/intel/quark/fsp2_0.c
index dccd28ef85..deb933427d 100644
--- a/src/soc/intel/quark/fsp2_0.c
+++ b/src/soc/intel/quark/fsp2_0.c
@@ -19,3 +19,7 @@
 void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd)
 {
 }
+
+asmlinkage void chipset_teardown_car(void)
+{
+}
diff --git a/src/soc/intel/quark/include/soc/pm.h b/src/soc/intel/quark/include/soc/pm.h
index 7547a53605..55e5e956aa 100644
--- a/src/soc/intel/quark/include/soc/pm.h
+++ b/src/soc/intel/quark/include/soc/pm.h
@@ -25,6 +25,10 @@ struct chipset_power_state {
 } __attribute__ ((packed));
 
 struct chipset_power_state *get_power_state(void);
+#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 struct chipset_power_state *fill_power_state(void);
-
+#else
+int fill_power_state(void);
 #endif
+
+#endif /* _SOC_PM_H_ */
diff --git a/src/soc/intel/quark/include/soc/ramstage.h b/src/soc/intel/quark/include/soc/ramstage.h
index d97db747c3..0ff21286e4 100644
--- a/src/soc/intel/quark/include/soc/ramstage.h
+++ b/src/soc/intel/quark/include/soc/ramstage.h
@@ -28,5 +28,6 @@ void mainboard_gpio_i2c_init(device_t dev);
 #if IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)
 void fsp_silicon_init(void);
 #endif
+asmlinkage void chipset_teardown_car(void);
 
 #endif /* _SOC_RAMSTAGE_H_ */
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 329138b3be..3a33f43c13 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -15,8 +15,11 @@
 
 romstage-y += car.c
 romstage-y += car_stage_entry.S
-romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
+ifeq ($(CONFIG_PLATFORM_USES_FSP2_0),y)
+romstage-$(CONFIG_DISPLAY_UPD_DATA) += debug.c
 romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0.c
+endif # CONFIG_PLATFORM_USES_FSP2_0
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
 romstage-y += mtrr.c
 romstage-y += pcie.c
 romstage-y += report_platform.c
diff --git a/src/soc/intel/quark/romstage/debug.c b/src/soc/intel/quark/romstage/debug.c
new file mode 100644
index 0000000000..c08150e575
--- /dev/null
+++ b/src/soc/intel/quark/romstage/debug.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <fsp/util.h>
+
+void soc_display_fspm_upd_params(const struct FSPM_UPD *fspm_old_upd,
+	const struct FSPM_UPD *fspm_new_upd)
+{
+	const struct FSP_M_CONFIG *new;
+	const struct FSP_M_CONFIG *old;
+
+	old = &fspm_old_upd->FspmConfig;
+	new = &fspm_new_upd->FspmConfig;
+
+	/* Display the parameters for MemoryInit */
+	printk(BIOS_SPEW, "UPD values for MemoryInit at: 0x%p\n", new);
+	fsp_display_upd_value("AddrMode", sizeof(old->AddrMode),
+		old->AddrMode, new->AddrMode);
+	fsp_display_upd_value("ChanMask", sizeof(old->ChanMask),
+		old->ChanMask, new->ChanMask);
+	fsp_display_upd_value("ChanWidth", sizeof(old->ChanWidth),
+		old->ChanWidth, new->ChanWidth);
+	fsp_display_upd_value("DramDensity", sizeof(old->DramDensity),
+		old->DramDensity, new->DramDensity);
+	fsp_display_upd_value("DramRonVal", sizeof(old->DramRonVal),
+		old->DramRonVal, new->DramRonVal);
+	fsp_display_upd_value("DramRttNomVal", sizeof(old->DramRttNomVal),
+		old->DramRttNomVal, new->DramRttNomVal);
+	fsp_display_upd_value("DramRttWrVal", sizeof(old->DramRttWrVal),
+		old->DramRttWrVal, new->DramRttWrVal);
+	fsp_display_upd_value("DramSpeed", sizeof(old->DramSpeed),
+		old->DramSpeed, new->DramSpeed);
+	fsp_display_upd_value("DramType", sizeof(old->DramType),
+		old->DramType, new->DramType);
+	fsp_display_upd_value("DramWidth", sizeof(old->DramWidth),
+		old->DramWidth, new->DramWidth);
+	fsp_display_upd_value("EccScrubBlkSize", sizeof(old->EccScrubBlkSize),
+		old->EccScrubBlkSize, new->EccScrubBlkSize);
+	fsp_display_upd_value("EccScrubInterval", sizeof(old->EccScrubInterval),
+		old->EccScrubInterval, new->EccScrubInterval);
+	fsp_display_upd_value("Flags", sizeof(old->Flags), old->Flags,
+		new->Flags);
+	fsp_display_upd_value("FspReservedMemoryLength",
+		sizeof(old->FspReservedMemoryLength),
+		old->FspReservedMemoryLength, new->FspReservedMemoryLength);
+	fsp_display_upd_value("RankMask", sizeof(old->RankMask), old->RankMask,
+		new->RankMask);
+	fsp_display_upd_value("RmuBaseAddress", sizeof(old->RmuBaseAddress),
+		old->RmuBaseAddress, new->RmuBaseAddress);
+	fsp_display_upd_value("RmuLength", sizeof(old->RmuLength),
+		old->RmuLength, new->RmuLength);
+	fsp_display_upd_value("SerialPortBaseAddress",
+		sizeof(old->SerialPortBaseAddress),
+		old->SerialPortBaseAddress, new->SerialPortBaseAddress);
+	fsp_display_upd_value("SmmTsegSize", sizeof(old->SmmTsegSize),
+		old->SmmTsegSize, new->SmmTsegSize);
+	fsp_display_upd_value("SocRdOdtVal", sizeof(old->SocRdOdtVal),
+		old->SocRdOdtVal, new->SocRdOdtVal);
+	fsp_display_upd_value("SocWrRonVal", sizeof(old->SocWrRonVal),
+		old->SocWrRonVal, new->SocWrRonVal);
+	fsp_display_upd_value("SocWrSlewRate", sizeof(old->SocWrSlewRate),
+		old->SocWrSlewRate, new->SocWrSlewRate);
+	fsp_display_upd_value("SrInt", sizeof(old->SrInt), old->SrInt,
+		new->SrInt);
+	fsp_display_upd_value("SrTemp", sizeof(old->SrTemp), old->SrTemp,
+		new->SrTemp);
+	fsp_display_upd_value("tCL", sizeof(old->tCL), old->tCL, new->tCL);
+	fsp_display_upd_value("tFAW", sizeof(old->tFAW), old->tFAW, new->tFAW);
+	fsp_display_upd_value("tRAS", sizeof(old->tRAS), old->tRAS, new->tRAS);
+	fsp_display_upd_value("tRRD", sizeof(old->tRRD), old->tRRD, new->tRRD);
+	fsp_display_upd_value("tWTR", sizeof(old->tWTR), old->tWTR, new->tWTR);
+}
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c
index a77349897d..af05856ab0 100644
--- a/src/soc/intel/quark/romstage/fsp2_0.c
+++ b/src/soc/intel/quark/romstage/fsp2_0.c
@@ -13,13 +13,165 @@
  * GNU General Public License for more details.
  */
 
+#include <arch/early_variables.h>
 #include <console/console.h>
+#include <cbfs.h>
+#include <cbmem.h>
+#include "../chip.h"
+#include <cpu/x86/cache.h>
 #include <fsp/util.h>
+#include <soc/iomap.h>
+#include <soc/pci_devs.h>
+#include <soc/pm.h>
 #include <soc/romstage.h>
+#include <soc/reg_access.h>
 
 asmlinkage void *car_stage_c_entry(void)
 {
+	struct postcar_frame pcf;
+	bool s3wake;
+	uintptr_t top_of_ram;
+	uintptr_t top_of_low_usable_memory;
+
 	post_code(0x20);
 	console_init();
+
+	/* Initialize DRAM */
+	s3wake = fill_power_state() == ACPI_S3;
+	fsp_memory_init(s3wake);
+
+	/* Disable the ROM shadow 0x000e0000 - 0x000fffff */
+	disable_rom_shadow();
+
+	/* Initialize the PCIe bridges */
+	pcie_init();
+
+	if (postcar_frame_init(&pcf, 1*KiB))
+		die("Unable to initialize postcar frame.\n");
+
+	/* Locate the top of RAM */
+	top_of_low_usable_memory = (uintptr_t) cbmem_top();
+	top_of_ram = ALIGN(top_of_low_usable_memory, 16 * MiB);
+
+	/* Cache postcar and ramstage */
+	postcar_frame_add_mtrr(&pcf, top_of_ram - (16 * MiB), 16 * MiB,
+		MTRR_TYPE_WRBACK);
+
+	/* Cache RMU area */
+	postcar_frame_add_mtrr(&pcf, (uintptr_t) top_of_low_usable_memory,
+		0x10000, MTRR_TYPE_WRTHROUGH);
+
+	/* Cache ESRAM */
+	postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
+
+	/* Cache SPI flash - Write protect not supported */
+	postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE),
+		CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH);
+
+	run_postcar_phase(&pcf);
 	return NULL;
 }
+
+static struct chipset_power_state power_state CAR_GLOBAL;
+
+struct chipset_power_state *get_power_state(void)
+{
+	return (struct chipset_power_state *)car_get_var_ptr(&power_state);
+}
+
+int fill_power_state(void)
+{
+	struct chipset_power_state *ps = get_power_state();
+
+	ps->prev_sleep_state = 0;
+	printk(BIOS_SPEW, "prev_sleep_state %d\n", ps->prev_sleep_state);
+	return ps->prev_sleep_state;
+}
+
+void platform_fsp_memory_init_params_cb(struct FSPM_UPD *fspm_upd)
+{
+	struct FSPM_ARCH_UPD *aupd;
+	const struct device *dev;
+	const struct soc_intel_quark_config *config;
+	char *rmu_file;
+	size_t rmu_file_len;
+	struct FSP_M_CONFIG *upd;
+
+	/* Clear SMI and wake events */
+	clear_smi_and_wake_events();
+
+	/* Locate the RMU data file in flash */
+	rmu_file = cbfs_boot_map_with_leak("rmu.bin", CBFS_TYPE_RAW,
+		&rmu_file_len);
+	if (!rmu_file)
+		die("Microcode file (rmu.bin) not found.");
+
+	/* Locate the configuration data from devicetree.cb */
+	dev = dev_find_slot(0, LPC_DEV_FUNC);
+	if (!dev) {
+		die("ERROR - LPC device not found!");
+	}
+	config = dev->chip_info;
+
+	/* Update the architectural UPD values. */
+	aupd = &fspm_upd->FspmArchUpd;
+	aupd->BootLoaderTolumSize = cbmem_overhead_size();
+	aupd->StackBase = (void *)(CONFIG_FSP_ESRAM_LOC - aupd->StackSize);
+	aupd->BootMode = FSP_BOOT_WITH_FULL_CONFIGURATION;
+
+	/* Display the ESRAM layout */
+	if (IS_ENABLED(CONFIG_DISPLAY_ESRAM_LAYOUT)) {
+		printk(BIOS_SPEW, "\nESRAM Layout:\n\n");
+		printk(BIOS_SPEW,
+			"+-------------------+ 0x80080000 - ESRAM end\n");
+		printk(BIOS_SPEW, "| FSP binary        |\n");
+		printk(BIOS_SPEW,
+			"+-------------------+ 0x%08x (CONFIG_FSP_ESRAM_LOC)\n",
+			CONFIG_FSP_ESRAM_LOC);
+		printk(BIOS_SPEW, "| FSP stack         |\n");
+		printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+			aupd->StackBase);
+		printk(BIOS_SPEW, "|                   |\n");
+		printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+			_car_relocatable_data_end);
+		printk(BIOS_SPEW, "| coreboot data     |\n");
+		printk(BIOS_SPEW, "+-------------------+ 0x%p\n",
+			_car_stack_end);
+		printk(BIOS_SPEW, "| coreboot stack    |\n");
+		printk(BIOS_SPEW,
+			"+-------------------+ 0x80000000 - ESRAM start\n\n");
+	}
+
+	/* Update the UPD data for MemoryInit */
+	upd = &fspm_upd->FspmConfig;
+	upd->AddrMode = config->AddrMode;
+	upd->ChanMask = config->ChanMask;
+	upd->ChanWidth = config->ChanWidth;
+	upd->DramDensity = config->DramDensity;
+	upd->DramRonVal = config->DramRonVal;
+	upd->DramRttNomVal = config->DramRttNomVal;
+	upd->DramRttWrVal = config->DramRttWrVal;
+	upd->DramSpeed = config->DramSpeed;
+	upd->DramType = config->DramType;
+	upd->DramWidth = config->DramWidth;
+	upd->EccScrubBlkSize = config->EccScrubBlkSize;
+	upd->EccScrubInterval = config->EccScrubInterval;
+	upd->Flags = config->Flags;
+	upd->FspReservedMemoryLength = config->FspReservedMemoryLength;
+	upd->RankMask = config->RankMask;
+	upd->RmuBaseAddress = (uintptr_t)rmu_file;
+	upd->RmuLength = rmu_file_len;
+	upd->SerialPortBaseAddress = UART_BASE_ADDRESS;
+	upd->SmmTsegSize = IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) ?
+		config->SmmTsegSize : 0;
+	upd->SocRdOdtVal = config->SocRdOdtVal;
+	upd->SocWrRonVal = config->SocWrRonVal;
+	upd->SocWrSlewRate = config->SocWrSlewRate;
+	upd->SrInt = config->SrInt;
+	upd->SrTemp = config->SrTemp;
+	upd->tCL = config->tCL;
+	upd->tFAW = config->tFAW;
+	upd->tRAS = config->tRAS;
+	upd->tRRD = config->tRRD;
+	upd->tWTR = config->tWTR;
+}