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| author | Matt DeVillier <matt.devillier@gmail.com> | 2018-03-04 01:44:15 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2018-03-08 19:14:17 +0000 |
| commit | a51e379eaff3652dc64e23bb0d3784222a38723a (patch) | |
| tree | 5296bfb357dddedc61f585f3bf36c14b351b6044 /src/soc/intel/quark | |
| parent | 8a6377ec24c85bc6a18eb9c57045746d2261ce1a (diff) | |
nb/intel/haswell;sb/intel/lynxpoint: Enable VT-d and X2APIC
We use the usual static addresses 0xfed90000/0xfed91000 for the GFX
IOMMU and the general IOMMU respectively. These addresses have to be
configured in MCHBAR registers and reserved from the OS.
GFXVTBAR/VTVC0BAR policy registers set to be consistent with
proprietary vendor firmwares on hardware of same platform
(2 different vendor firmwares compared, found to be identical).
Change-Id: Ib8f2fed9ae08491779e76f7d1ddc1bd3eed45ac7
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/24983
Reviewed-by: Youness Alaoui <snifikino@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark')
0 files changed, 0 insertions, 0 deletions