soc/intel/meteorlake: Move P2SB PCI resource into P2SB device

This patch ensures the P2SB PCI device resource is getting reserved
so that the resource allocator is not assigning this resource to any
other PCI device during the PCI enumeration.

BUG=b:254207628
TEST=Able to ensure on the Google/Rex device, the PCI enumeration
is not assigning the P2SB BAR (0xE000_0000) to TBT Root Port3.
Instead the 0xE000_0000 address is being assigned to the P2SB
PCI device.

Without this patch:
[SPEW ]     PCI: 00:07.3 resource base e0000000 size c200000 align
            20 gran 20 limit ec1fffff flags 60080202 index 20
[DEBUG]      GENERIC: 1.0
[DEBUG]      NONE
[SPEW ]      NONE resource base e0000000 size c200000 align 12 gran
             12 limit ec1fffff flags 40000200 index 10

With this patch:
[SPEW ]     PCI: 00:07.3 resource base e1000000 size c200000 align
            20 gran 20 limit ed1fffff flags 60080202 index 20
[DEBUG]      GENERIC: 1.0
[DEBUG]      NONE
[SPEW ]      NONE resource base e1000000 size c200000 align 12 gran
             12 limit ed1fffff flags 40000200 index 10
......
[DEBUG]     PCI: 00:1f.1
[SPEW ]     PCI: 00:1f.1 resource base e0000000 size 1000000 align
            0 gran 0 limit 0 flags f0000200 index 10

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ib0789b442af23f6be81c666e284633ef342dffe0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68909
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Tarun Tuli <taruntuli@google.com>

0 files changed, 0 insertions, 0 deletions