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authorTim Wawrzynczak <twawrzynczak@chromium.org>2021-12-08 10:43:56 -0700
committerTim Wawrzynczak <twawrzynczak@chromium.org>2022-01-07 20:00:09 +0000
commitb6a15a72276c0110ad8828c91849ff9864ae115e (patch)
treec6c5778b3a3528ee40e10ae3894ed9dcb83baedb /src/soc/intel/quark/uart.c
parentf94405219c93613471a33db9a76bb6106469eb1b (diff)
soc/intel/common/block/pcie/rtd3: Update ACPI methods for CPU PCIe RPs
The PMC IPC method that is used for RTD3 support expects to be provided the virtual wire index instead of the LCAP PN for CPU PCIe RPs. Therefore, use the prior patches to update pcie_rp for CPU RPs. Note that an unused argument to pcie_rtd3_acpi_method_status() was also dropped. BUG=b:197983574 TEST=add rtd3 node under pcie4_0 in overridetree for brya0, boot and inspect the SSDT to see the PMC IPC parameters are as expected for the CPU RP, and the ModPhy power gating code is not found in the AML for the PEG port. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Crawford <tcrawford@system76.com> Change-Id: I84a1affb32cb53e686dbe825d3c3a424715df873 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60183 Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark/uart.c')
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