diff options
| author | Nico Huber <nico.h@gmx.de> | 2018-05-27 14:01:11 +0200 |
|---|---|---|
| committer | Nico Huber <nico.h@gmx.de> | 2018-05-31 15:11:21 +0000 |
| commit | 9593e973fa0e3a104837d1df9659b3992d915b34 (patch) | |
| tree | 8f0aace9603886d215e22c294355a9e5b769133d /src/soc/intel/quark/romstage | |
| parent | 654cc2fe109ea1be4d22447b3d0e6eb22a75b550 (diff) | |
soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)
Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.
Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark/romstage')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 10e44c1b68..74796448c4 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -80,8 +80,8 @@ asmlinkage void *car_stage_c_entry(void) postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); /* Cache SPI flash - Write protect not supported */ - postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE), - CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH); + postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE, + MTRR_TYPE_WRTHROUGH); run_postcar_phase(&pcf); return NULL; |