soc/intel/quark: Add PCIe reset support

Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.

Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

3 files changed, 113 insertions, 0 deletions

diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index fc7bd6aeb4..2f29b06a70 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -17,6 +17,7 @@ cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
 cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
 
 romstage-y += mtrr.c
+romstage-y += pcie.c
 romstage-y += report_platform.c
 romstage-y += romstage.c
 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c
diff --git a/src/soc/intel/quark/romstage/pcie.c b/src/soc/intel/quark/romstage/pcie.c
new file mode 100644
index 0000000000..f2adc18e86
--- /dev/null
+++ b/src/soc/intel/quark/romstage/pcie.c
@@ -0,0 +1,109 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2016 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <delay.h>
+#include <device/device.h>
+#include <device/pci_ids.h>
+#include <soc/pci_devs.h>
+#include <soc/reg_access.h>
+#include <soc/romstage.h>
+
+/* Minimum time in microseconds for assertion of PERST# signal */
+#define PCIEXP_PERST_MIN_ASSERT_US		100
+
+/* Microsecond delay post issuing common lane reset */
+#define PCIEXP_DELAY_US_POST_CMNRESET_RESET	1
+
+/* Microsecond delay to wait for PLL to lock */
+#define PCIEXP_DELAY_US_WAIT_PLL_LOCK		80
+
+/* Microsecond delay post issuing sideband interface reset */
+#define PCIEXP_DELAY_US_POST_SBI_RESET		20
+
+/* Microsecond delay post deasserting PERST# */
+#define PCIEXP_DELAY_US_POST_PERST_DEASSERT	10
+
+const struct reg_script pcie_init_script[] = {
+	/* Assert PCIe reset# */
+	MAINBOARD_PCIE_RESET(0),
+
+	/* PHY Common lane reset */
+	REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
+		SOCCLKEN_CONFIG_PHY_I_CMNRESET_L),
+
+	/* Wait post common lane reset */
+	TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_CMNRESET_RESET),
+
+	/* PHY Sideband interface reset.
+	 * Controller main reset
+	 */
+	REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
+		SOCCLKEN_CONFIG_SBI_RST_100_CORE_B
+		| SOCCLKEN_CONFIG_PHY_I_SIDE_RST_L),
+	TIME_DELAY_USEC(PCIEXP_DELAY_US_WAIT_PLL_LOCK),
+
+	/* Controller sideband interface reset */
+	REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
+		SOCCLKEN_CONFIG_SBI_BB_RST_B),
+
+	/* Wait post sideband interface reset */
+	TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_SBI_RESET),
+
+	/* Deassert PCIe reset# */
+	MAINBOARD_PCIE_RESET(1),
+
+	/* Wait post de assert PERST#. */
+	TIME_DELAY_USEC(PCIEXP_DELAY_US_POST_PERST_DEASSERT),
+
+	/* Controller primary interface reset */
+	REG_SOC_UNIT_OR(QUARK_SCSS_SOC_UNIT_SOCCLKEN_CONFIG,
+		SOCCLKEN_CONFIG_BB_RST_B),
+
+	/* Set the mixer load resistance */
+	REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L0,
+		OCFGPIMIXLOAD_1_0_MASK),
+	REG_PCIE_AFE_AND(QUARK_PCIE_AFE_PCIE_RXPICTRL0_L1,
+		OCFGPIMIXLOAD_1_0_MASK),
+	REG_SCRIPT_END
+};
+
+static const struct reg_script pcie_bus_init_script[] = {
+	/* Setup Message Bus Idle Counter (SBIC) values */
+	REG_PCI_RMW8(R_QNC_PCIE_IOSFSBCTL, ~B_QNC_PCIE_IOSFSBCTL_SBIC_MASK,
+		V_PCIE_ROOT_PORT_SBIC_VALUE),
+	REG_PCI_READ8(R_QNC_PCIE_IOSFSBCTL),
+
+	/* Set the IPF bit in MCR2 */
+	REG_PCI_OR32(R_QNC_PCIE_MPC2, B_QNC_PCIE_MPC2_IPF),
+	REG_PCI_READ32(R_QNC_PCIE_MPC2),
+
+	/* Set up the Posted and Non Posted Request sizes for PCIe */
+	REG_PCI_RMW32(R_QNC_PCIE_CCFG, ~B_QNC_PCIE_CCFG_UPSD,
+		(B_QNC_PCIE_CCFG_UNRS | B_QNC_PCIE_CCFG_UPRS)),
+	REG_PCI_READ32(R_QNC_PCIE_CCFG),
+	REG_SCRIPT_END
+};
+
+void pcie_init(void)
+{
+	/* Initialize the PCIe bridges */
+	printk(BIOS_DEBUG, "Initializing PCIe controllers\n");
+	reg_script_run(pcie_init_script);
+	printk(BIOS_DEBUG, "Initializing PCIe bus 0\n");
+	reg_script_run_on_dev(PCIE_PORT0_BDF, pcie_bus_init_script);
+	printk(BIOS_DEBUG, "Initializing PCIe bus 1\n");
+	reg_script_run_on_dev(PCIE_PORT1_BDF, pcie_bus_init_script);
+}
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 2f16c5f37a..4ed5863179 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -125,6 +125,9 @@ void soc_after_ram_init(struct romstage_params *params)
 
 	/* Display the DRAM data */
 	hexdump((void *)0x000ffff0, 0x10);
+
+	/* Initialize the PCIe bridges */
+	pcie_init();
 }
 
 void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,