diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-02 14:31:02 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-04 22:36:53 +0200 |
| commit | 4dd34eee092276e47a9be41ff9a51dfcde38d759 (patch) | |
| tree | abdacd55254200959e82094f6f9c0bf962235661 /src/soc/intel/quark/romstage | |
| parent | 5c4ddebb1631165f9bd36f6ea629b39a290afff4 (diff) | |
soc/intel/quark: Add USB PHY initialization
Add register access support using register scripts.
Initialize the USB PHY using register scripts.
TEST=Build and run on Galileo Gen2
Change-Id: I34a8e78eab3c7314ca34343eccc8aeef0622798a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14496
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage')
| -rw-r--r-- | src/soc/intel/quark/romstage/mtrr.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index 8b237a35e0..f03be1d1e2 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -21,31 +21,6 @@ #include <soc/pci_devs.h> #include <soc/romstage.h> -void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MCR, - (opcode << QNC_MCR_OP_OFFSET) - | ((uint32_t)port << QNC_MCR_PORT_OFFSET) - | ((reg_address & QNC_MCR_MASK) << QNC_MCR_REG_OFFSET) - | QNC_MCR_BYTE_ENABLES); -} - -uint32_t mdr_read(void) -{ - return pci_read_config32(MC_BDF, QNC_ACCESS_PORT_MDR); -} - -void mdr_write(uint32_t value) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MDR, value); -} - -void mea_write(uint32_t reg_address) -{ - pci_write_config32(MC_BDF, QNC_ACCESS_PORT_MEA, reg_address - & QNC_MEA_MASK); -} - static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) { uint32_t offset; |