diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-03-04 16:49:40 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-03-21 19:46:59 +0100 |
| commit | d75ed0bfd9238b210fdca136784cd699696421c7 (patch) | |
| tree | 403700be6619d403c68bbd866f5cdc47195fdfbf /src/soc/intel/quark/romstage/romstage.c | |
| parent | 1f1f2c4d38dc5b58e0051f9d80086bc2a083a7cd (diff) | |
soc/intel/quark: Disable the ROM shadow
Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Testing successful display of 0x000ffff0 - 0x000fffff does not match
the end of the SPI flash.
Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14110
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index a089185bd0..5bedb25b3b 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <fsp/car.h> #include <fsp/util.h> +#include <lib.h> #include <soc/intel/common/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -86,6 +87,30 @@ void soc_memory_init_params(struct romstage_params *params, config->PcdSmmTsegSize : 0; upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; + + /* Display the ROM shadow data */ + hexdump((void *)0x000ffff0, 0x10); +} + +void soc_after_ram_init(struct romstage_params *params) +{ + uint32_t data; + + /* Determine if the shadow ROM is enabled */ + data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + QNC_MSG_FSBIC_REG_HMISC); + printk(BIOS_DEBUG, "0x%08x: HMISC\n", data); + if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM)) + != (ESEG_RD_DRAM | FSEG_RD_DRAM)) { + + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + data |= ESEG_RD_DRAM | FSEG_RD_DRAM; + port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + QNC_MSG_FSBIC_REG_HMISC, data); + } + + /* Display the DRAM data */ + hexdump((void *)0x000ffff0, 0x10); } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, |