soc/intel/quark: Add C bootblock

Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0.  Move esraminit from
romstage into the bootblock.  Replace cache_as_ram with
car_stage_entry.S and code in romstage.c

TEST=Build and run on Galileo Gen2

Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c
index 62f8b212e5..c14acb768e 100644
--- a/src/soc/intel/quark/romstage/romstage.c
+++ b/src/soc/intel/quark/romstage/romstage.c
@@ -29,6 +29,7 @@
 #include <soc/pm.h>
 #include <soc/romstage.h>
 #include <soc/reg_access.h>
+#include <string.h>
 
 static const struct reg_script clear_smi_and_wake_events[] = {
 	/* Clear any SMI or wake events */
@@ -65,6 +66,33 @@ static const struct reg_script hsuart_init[] = {
 	REG_SCRIPT_END
 };
 
+asmlinkage void *car_state_c_entry(void)
+{
+	post_code(0x20);
+	if (IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1)) {
+		FSP_INFO_HEADER *fih;
+		struct cache_as_ram_params car_params = {0};
+		void *top_of_stack;
+
+		/* Copy the FSP binary into ESRAM */
+		memcpy((void *)CONFIG_FSP_ESRAM_LOC, (void *)CONFIG_FSP_LOC,
+			0x00040000);
+
+		/* Locate the FSP header in ESRAM */
+		fih = find_fsp(CONFIG_FSP_ESRAM_LOC);
+
+		/* Start the early verstage/romstage code */
+		post_code(0x2A);
+		car_params.fih = fih;
+		top_of_stack = cache_as_ram_main(&car_params);
+
+		/* Initialize MTRRs and switch stacks after RAM initialized */
+		return top_of_stack;
+	}
+
+	return NULL;
+}
+
 void car_soc_pre_console_init(void)
 {
 	/* Initialize the controllers */