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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-04-29 15:16:54 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-31 21:50:31 +0200 |
| commit | 5ef051a53a03d537b6feab4e85edb69835eb6998 (patch) | |
| tree | eb2c8089bf5fc987f6bafe4587be4db0aef66005 /src/soc/intel/quark/romstage/romstage.c | |
| parent | a87fcabd2efe49c8035b76146401e190a0ea6593 (diff) | |
soc/intel/quark: Add PCIe reset support
Migrate PCIe reset from PlatformPciHelperLib in QuarkFspPkg into
coreboot.
Change-Id: I1c33fa16b0323091e8f9bd503bbfdb8a253a76d4
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14944
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/romstage.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/romstage.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index 2f16c5f37a..4ed5863179 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -125,6 +125,9 @@ void soc_after_ram_init(struct romstage_params *params) /* Display the DRAM data */ hexdump((void *)0x000ffff0, 0x10); + + /* Initialize the PCIe bridges */ + pcie_init(); } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, |