diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-20 08:58:58 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-03 17:47:53 +0200 |
| commit | 01728bb2ed1847dadf1429fafe0be2cb7876eed8 (patch) | |
| tree | dac9a0682b205409038d4b742350ba28e2dc1af3 /src/soc/intel/quark/romstage/mtrr.c | |
| parent | 3d0e3cf4b125dfda236d6978adea5f5d40fd78e8 (diff) | |
soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.
TEST=Build and run on Galileo Gen2
Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/romstage/mtrr.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/mtrr.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index ce5bd4acb5..e6bb51fd25 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -19,7 +19,7 @@ #include <cpu/x86/mtrr.h> #include <soc/intel/common/util.h> #include <soc/pci_devs.h> -#include <soc/romstage.h> +#include <soc/reg_access.h> asmlinkage void *soc_set_mtrrs(void *top_of_stack) { |