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author | Nico Huber <nico.h@gmx.de> | 2018-05-27 13:52:28 +0200 |
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committer | Nico Huber <nico.h@gmx.de> | 2018-05-31 15:10:21 +0000 |
commit | 654cc2fe109ea1be4d22447b3d0e6eb22a75b550 (patch) | |
tree | df38c7f7fae159a0549c31acd39b4dd8648fc538 /src/soc/intel/quark/romstage/fsp2_0.c | |
parent | 6197b7698875271a2b72e730040ec7e9260a454c (diff) |
{cpu,drivers,nb,soc}/intel: Use CACHE_ROM_BASE where appropriate
Change-Id: Ibc2392cd2a00fde3e15dda4d44c8b6874d7ac8a3
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26574
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp2_0.c')
0 files changed, 0 insertions, 0 deletions