diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-06 08:59:23 -0800 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2017-03-07 18:31:04 +0100 |
| commit | 94b971a909d7b9695a8a5b28eed2296f0e7cabb2 (patch) | |
| tree | fd6a0c591eb3b26087f9dd9f7dfb14dc5f3f9e50 /src/soc/intel/quark/romstage/fsp2_0.c | |
| parent | a24c81cd304c10911a8aae75f9d95bc1fa9574ca (diff) | |
soc/intel/quark: Fix errors detected by checkpatch
Fix the errors detected by checkpatch and update the copyright dates.
TEST=Build and run on Galileo Gen2
Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18591
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp2_0.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp2_0.c | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/soc/intel/quark/romstage/fsp2_0.c b/src/soc/intel/quark/romstage/fsp2_0.c index 17080a3baf..4d7f7c9479 100644 --- a/src/soc/intel/quark/romstage/fsp2_0.c +++ b/src/soc/intel/quark/romstage/fsp2_0.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. + * Copyright (C) 2016-2017 Intel Corp. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -107,9 +107,8 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *fspm_upd, uint32_t version) /* Locate the configuration data from devicetree.cb */ dev = dev_find_slot(0, LPC_DEV_FUNC); - if (!dev) { + if (!dev) die("ERROR - LPC device not found!"); - } config = dev->chip_info; /* Update the architectural UPD values. */ |