diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-25 07:41:54 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-05 01:50:45 +0200 |
| commit | 102f6253600cfa3f741c0d1d126436d612daa203 (patch) | |
| tree | dc3d0c6376b405dc053e4f4c9c864d30cf4737eb /src/soc/intel/quark/romstage/fsp1_1.c | |
| parent | 6e05c33626e128c383470579f423b1ee569302ba (diff) | |
soc/intel/quark: Add FSP 2.0 boot block support
Add the pieces necessary to successfully build and run bootblock using
the FSP 2.0 build.
TEST=Build and run bootblock on Galileo Gen2
Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15865
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/fsp1_1.c')
| -rw-r--r-- | src/soc/intel/quark/romstage/fsp1_1.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/fsp1_1.c b/src/soc/intel/quark/romstage/fsp1_1.c index 73910a0775..16d1d063c3 100644 --- a/src/soc/intel/quark/romstage/fsp1_1.c +++ b/src/soc/intel/quark/romstage/fsp1_1.c @@ -19,9 +19,11 @@ #include <console/console.h> #include <cbfs.h> #include "../chip.h" +#include <fsp/memmap.h> #include <fsp/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> +#include <soc/QuarkNcSocId.h> #include <soc/romstage.h> #include <string.h> @@ -65,6 +67,12 @@ struct chipset_power_state *fill_power_state(void) return ps; } +size_t mmap_region_granularity(void) +{ + /* Align to 8 MiB by default */ + return 8 << 20; +} + /* Initialize the UPD parameters for MemoryInit */ void soc_memory_init_params(struct romstage_params *params, MEMORY_INIT_UPD *upd) |