diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-07 14:37:13 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-09 16:20:38 +0100 |
| commit | 87df8d08d676f79b894da84ebe6f8a57f69ba5b1 (patch) | |
| tree | c631ba642e44184808868342efd8055ec30731aa /src/soc/intel/quark/romstage/cache_as_ram.inc | |
| parent | 5d7df71cfe6c5a4c8615f33d194cb34947f53c05 (diff) | |
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/quark/romstage/cache_as_ram.inc')
| -rw-r--r-- | src/soc/intel/quark/romstage/cache_as_ram.inc | 41 |
1 files changed, 40 insertions, 1 deletions
diff --git a/src/soc/intel/quark/romstage/cache_as_ram.inc b/src/soc/intel/quark/romstage/cache_as_ram.inc index d323f03b51..4fc60e284b 100644 --- a/src/soc/intel/quark/romstage/cache_as_ram.inc +++ b/src/soc/intel/quark/romstage/cache_as_ram.inc @@ -115,7 +115,46 @@ CAR_init_done: #endif /* CONFIG_ENABLE_DEBUG_LED_TEMPRAMINIT */ /* Set up bootloader stack */ - clrl %eax + movl %edx, %esp + + /* + * eax: 0 + * ebp: FSP_INFO_HEADER address + * ecx: Temp RAM base + * edx: Temp RAM top + * edi: BIST value + * esp: Top of stack in temp RAM + */ + + /* Create cache_as_ram_params on stack */ + pushl %edx /* bootloader CAR end */ + pushl %ecx /* bootloader CAR begin */ + pushl %ebp /* FSP_INFO_HEADER */ + pushl $0 /* BIST - esram_init.inc catches non-zero BIST values */ + /* TODO: Locate 64-bits of storage for initial TSC value */ + pushl $0 /* tsc[63:32] */ + pushl $0 /* tsc[31:0] */ + pushl %esp /* pointer to cache_as_ram_params */ + + /* Save FSP_INFO_HEADER location in ebx */ + mov %ebp, %ebx + + /* Coreboot assumes stack/heap region will be zero */ + cld + movl %ecx, %edi + neg %ecx + /* Only clear up to current stack value. */ + add %esp, %ecx + shrl $2, %ecx + xorl %eax, %eax + rep stosl + +before_romstage: + post_code(0x2A) + + /* Call cache_as_ram_main(struct cache_as_ram_params *) */ + call cache_as_ram_main + movb $0x69, %ah jmp .Lhlt halt1: |