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authorLee Leahy <leroy.p.leahy@intel.com>2016-03-03 16:48:22 -0800
committerMartin Roth <martinroth@google.com>2016-03-07 04:20:22 +0100
commitfba78bf8972b2fbc9e9089bc41226dcc79953804 (patch)
tree453d7d7ff5bf05ff0967a5e7b58f1b403e5ae1b3 /src/soc/intel/quark/romstage/Makefile.inc
parent6d3cd08252534dfe9a6f49ed772419d8765f0c71 (diff)
soc/intel/quark: Split out MTRR support
Split out the MTRR support into a new module: mtrr.c. TEST=Build and run on Galileo Change-Id: Ib9ec479d171dbbc062509e14fbe246f6d90e903a Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13895 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark/romstage/Makefile.inc')
-rw-r--r--src/soc/intel/quark/romstage/Makefile.inc1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 47972662a9..fc7bd6aeb4 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -16,6 +16,7 @@
cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc
cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc
+romstage-y += mtrr.c
romstage-y += report_platform.c
romstage-y += romstage.c
romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c