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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-05 18:48:31 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-12 14:52:44 +0200 |
| commit | ce9e21a0ea78039d80838071f9514c6a2ddaa8bc (patch) | |
| tree | a32c69c26338c0cea22e04628fb4b96465648744 /src/soc/intel/quark/romstage/Makefile.inc | |
| parent | 6c3c31e49d6b53d549de5c815ed9a2f7ab5a3521 (diff) | |
soc/intel/quark: Add C bootblock
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0. Move esraminit from
romstage into the bootblock. Replace cache_as_ram with
car_stage_entry.S and code in romstage.c
TEST=Build and run on Galileo Gen2
Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/romstage/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/romstage/Makefile.inc | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc index 6c92ac4474..16fc5ac9d8 100644 --- a/src/soc/intel/quark/romstage/Makefile.inc +++ b/src/soc/intel/quark/romstage/Makefile.inc @@ -13,9 +13,7 @@ # GNU General Public License for more details. # -cpu_incs-y += $(src)/soc/intel/quark/romstage/esram_init.inc -cpu_incs-y += $(src)/soc/intel/quark/romstage/cache_as_ram.inc - +romstage-y += car_stage_entry.S romstage-y += mtrr.c romstage-y += pcie.c romstage-y += report_platform.c |