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authorLee Leahy <leroy.p.leahy@intel.com>2016-07-20 08:58:58 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2016-08-03 17:47:53 +0200
commit01728bb2ed1847dadf1429fafe0be2cb7876eed8 (patch)
treedac9a0682b205409038d4b742350ba28e2dc1af3 /src/soc/intel/quark/romstage/Makefile.inc
parent3d0e3cf4b125dfda236d6978adea5f5d40fd78e8 (diff)
soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and fsp1_1.c. TEST=Build and run on Galileo Gen2 Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15862 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/romstage/Makefile.inc')
-rw-r--r--src/soc/intel/quark/romstage/Makefile.inc2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/quark/romstage/Makefile.inc b/src/soc/intel/quark/romstage/Makefile.inc
index 16fc5ac9d8..635da83c64 100644
--- a/src/soc/intel/quark/romstage/Makefile.inc
+++ b/src/soc/intel/quark/romstage/Makefile.inc
@@ -13,7 +13,9 @@
# GNU General Public License for more details.
#
+romstage-y += car.c
romstage-y += car_stage_entry.S
+romstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c
romstage-y += mtrr.c
romstage-y += pcie.c
romstage-y += report_platform.c