diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-30 18:21:53 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-03 18:03:46 +0200 |
| commit | 5fafc6ad540c12776d2cafa5bef0f5fca5b1e977 (patch) | |
| tree | e957649af477d5c9584655cbbcde650953e0a89f /src/soc/intel/quark/reg_access.c | |
| parent | 72fe7acbbb9ef81a30950accbc241e31fc772893 (diff) | |
soc/intel/quark: Support access to CPU CR registers
Add support to access CR0 and CR4.
TEST=Build and run on Galileo Gen2.
Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/reg_access.c')
| -rw-r--r-- | src/soc/intel/quark/reg_access.c | 38 |
1 files changed, 38 insertions, 0 deletions
diff --git a/src/soc/intel/quark/reg_access.c b/src/soc/intel/quark/reg_access.c index 368417b694..e5c0f0b6dc 100644 --- a/src/soc/intel/quark/reg_access.c +++ b/src/soc/intel/quark/reg_access.c @@ -141,6 +141,34 @@ void port_reg_write(uint8_t port, uint32_t offset, uint32_t value) mcr_write(QUARK_OPCODE_WRITE, port, offset); } +static CRx_TYPE reg_cpu_cr_read(uint32_t reg_address) +{ + /* Read the CPU CRx register */ + switch(reg_address) { + case 0: + return read_cr0(); + + case 4: + return read_cr4(); + } + die("ERROR - Unsupported CPU register!\n"); +} + +static void reg_cpu_cr_write(uint32_t reg_address, CRx_TYPE value) +{ + /* Write the CPU CRx register */ + switch(reg_address) { + default: + die("ERROR - Unsupported CPU register!\n"); + + case 0: + write_cr0(value); + + case 4: + write_cr4(value); + } +} + static uint32_t reg_gpe0_read(uint32_t reg_address) { /* Read the GPE0 register */ @@ -278,6 +306,11 @@ static uint64_t reg_read(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return 0; + case CPU_CR: + ctx->display_prefix = "CPU CR"; + value = reg_cpu_cr_read(step->reg); + break; + case GPE0_REGS: ctx->display_prefix = "GPE0"; value = reg_gpe0_read(step->reg); @@ -333,6 +366,11 @@ static void reg_write(struct reg_script_context *ctx) ctx->display_features = REG_SCRIPT_DISPLAY_NOTHING; return; + case CPU_CR: + ctx->display_prefix = "CPU CR"; + reg_cpu_cr_write(step->reg, step->value); + break; + case GPE0_REGS: ctx->display_prefix = "GPE0"; reg_gpe0_write(step->reg, (uint32_t)step->value); |