diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-05-22 11:52:28 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-05-31 21:57:55 +0200 |
| commit | 7f4b0539808ceea3854ad56cdc6f1cf69595279b (patch) | |
| tree | 4eb7958558f79c039aaa5c380558de4fbd885b10 /src/soc/intel/quark/include | |
| parent | 773ee2bb17344ebad1e99e997ff6700fc6479044 (diff) | |
soc/intel/quark: Clear SMI interrupts and wake events
Migrate the clearing of the SMI interrupts and wake events from FSP into
coreboot.
TEST=Build and run on Galileo Gen2
Change-Id: Ia369801da87a16bc00fb2c05475831ebe8a315f8
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/14945
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/iomap.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/quark/include/soc/reg_access.h | 22 |
2 files changed, 28 insertions, 3 deletions
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index ce92676c54..61773d5d4c 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -30,10 +30,13 @@ /* * I/O port address space */ -#define ACPI_BASE_ADDRESS 0x1000 -#define ACPI_BASE_SIZE 0x100 +#define GPE0_BASE_ADDRESS 0x2000 +#define GPE0_SIZE 0x40 -#define LEGACY_GPIO_BASE_ADDRESS 0x1080 +#define PM1BLK_BASE_ADDRESS 0x2040 +#define PM1BLK_SIZE 0x10 + +#define LEGACY_GPIO_BASE_ADDRESS 0x2080 #define LEGACY_GPIO_SIZE 0x80 #define IO_ADDRESS_VALID 0x80000000 diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 580400c331..e7a8963b8c 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -35,6 +35,7 @@ enum { GPIO_REGS, PCIE_AFE_REGS, PCIE_RESET, + GPE0_REGS, }; enum { @@ -46,6 +47,27 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* GPE0 controller register access macros */ +#define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + GPE0_REGS) +#define REG_GPE0_READ(reg_) \ + REG_GPE0_ACCESS(READ, reg_, 0, 0, 0) +#define REG_GPE0_WRITE(reg_, value_) \ + REG_GPE0_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_GPE0_AND(reg_, value_) \ + REG_GPE0_RMW(reg_, value_, 0) +#define REG_GPE0_RMW(reg_, mask_, value_) \ + REG_GPE0_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_GPE0_RXW(reg_, mask_, value_) \ + REG_GPE0_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_GPE0_OR(reg_, value_) \ + REG_GPE0_RMW(reg_, 0xffffffff, value_) +#define REG_GPE0_POLL(reg_, mask_, value_, timeout_) \ + REG_GPE0_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_GPE0_XOR(reg_, value_) \ + REG_GPE0_RXW(reg_, 0xffffffff, value_) + /* GPIO controller register access macros */ #define REG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ |