diff options
| author | Martin Roth <martin@coreboot.org> | 2021-10-01 14:53:22 -0600 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2021-10-05 18:07:08 +0000 |
| commit | 26f97f9532933da3c1d72a7918c8a24457bbc1c0 (patch) | |
| tree | 8c25279e58ef541fae197ec193f5642a9b21b2d4 /src/soc/intel/quark/include | |
| parent | 50863daef8ed75c0cb3dfd375e7622c898de5821 (diff) | |
src/soc to src/superio: Fix spelling errors
These issues were found and fixed by codespell, a useful tool for
finding spelling errors.
Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ieafbc93e49fcef198ac6e31fc8a3b708c395e08e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58082
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/QuarkNcSocId.h | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index c7db8d50b9..e4015a2e7c 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -55,7 +55,7 @@ // // -// DEVICE 0 (Memroy Controller Hub) +// DEVICE 0 (Memory Controller Hub) // #define MC_BUS PCI_BUS_NUMBER_QNC #define MC_DEV 0x00 @@ -729,7 +729,7 @@ #define V_QNC_PCIE_SLCAP_PSN_OFFSET 19 //Slot number offset #define R_QNC_PCIE_SLCTL 0x58 //~ 59h #define B_QNC_PCIE_SLCTL_HPE (BIT5) // Hot plug intr enable -#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presense detect enable +#define B_QNC_PCIE_SLCTL_PDE (BIT3) // Presence detect enable #define B_QNC_PCIE_SLCTL_ABE (BIT0) // Attn Btn Pressed Enable #define R_QNC_PCIE_SLSTS 0x5A //~ 5Bh #define B_QNC_PCIE_SLSTS_PDS (BIT6) // Present Detect State |