summaryrefslogtreecommitdiff
path: root/src/soc/intel/quark/include
diff options
context:
space:
mode:
authorLee Leahy <leroy.p.leahy@intel.com>2017-04-01 20:33:58 -0700
committerLee Leahy <leroy.p.leahy@intel.com>2017-05-08 19:13:35 +0200
commit16bc9bab2ab3b248f44bdf721ec83cdc21bcc32e (patch)
tree4d52e7ae44b49d4f63b21c74a255c47389e6bfeb /src/soc/intel/quark/include
parent52f29743b153e89ca38db5d7a207c676c4c70207 (diff)
soc/intel/quark: Add SD/MMC test support
The SD/MMC test support consists of: * Add Kconfig value to enable the SD/MMC test support. * Add Kconfig value to enable the logging support. * Add SD/MMC controller init code and read block 0 from each partition. * Add logging code to snapshot the transactions with the SD/MMC device. * Add eMMC driver for ramstage to call test code. * Add romstage code to call test code. * Add bootblock code to call test code. TEST=Build and run on Galileo Gen2 Change-Id: I72785f0dcd466c05c1385cef166731219b583551 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/19211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
-rw-r--r--src/soc/intel/quark/include/soc/iomap.h3
-rw-r--r--src/soc/intel/quark/include/soc/pci_devs.h2
-rw-r--r--src/soc/intel/quark/include/soc/storage_test.h53
3 files changed, 58 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h
index 1224bcc156..de81a1a030 100644
--- a/src/soc/intel/quark/include/soc/iomap.h
+++ b/src/soc/intel/quark/include/soc/iomap.h
@@ -28,6 +28,9 @@
#define I2C_BASE_ADDRESS 0xa0020000
#define GPIO_BASE_ADDRESS 0xa0021000
+/* Temporary BAR for SD controller */
+#define SD_BASE_ADDRESS 0xa0022000
+
/*
* I/O port address space
*/
diff --git a/src/soc/intel/quark/include/soc/pci_devs.h b/src/soc/intel/quark/include/soc/pci_devs.h
index fc28dfe1d1..a4e7a87fd2 100644
--- a/src/soc/intel/quark/include/soc/pci_devs.h
+++ b/src/soc/intel/quark/include/soc/pci_devs.h
@@ -33,8 +33,10 @@
/* IO Fabric 1 */
#define SIO1_DEV 0x14
+#define SD_MMC_DEV SIO1_DEV
#define HSUART0_DEV SIO1_DEV
#define HSUART1_DEV SIO1_DEV
+#define SD_MMC_FUNC 0
#define HSUART0_FUNC 1
#define USB_DEV_PORT_FUNC 2
#define EHCI_FUNC 3
diff --git a/src/soc/intel/quark/include/soc/storage_test.h b/src/soc/intel/quark/include/soc/storage_test.h
new file mode 100644
index 0000000000..6e970ccf3d
--- /dev/null
+++ b/src/soc/intel/quark/include/soc/storage_test.h
@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __STORAGE_TEST_H__
+#define __STORAGE_TEST_H__
+
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/sd_mmc_ctrlr.h>
+#include <timer.h>
+
+#ifdef __SIMPLE_DEVICE__
+#define dev_t uintptr_t
+#else
+#define dev_t device_t
+#endif /* __SIMPLE_DEVICE__ */
+
+uint32_t storage_test_init(dev_t dev, uint32_t *previous_bar,
+ uint16_t *previous_command);
+void storage_test(uint32_t bar, int full_initialization);
+void storage_test_complete(dev_t dev, uint32_t previous_bar,
+ uint16_t previous_command);
+
+/* Logging support */
+struct log_entry {
+ struct mono_time time;
+ struct mmc_command cmd;
+ int cmd_issued;
+ int ret;
+ uint32_t response_entries;
+ uint32_t response[4];
+};
+
+#define LOG_ENTRIES 256
+
+extern struct log_entry log[LOG_ENTRIES];
+extern uint8_t log_index;
+extern int log_full;
+extern long log_start_time;
+
+#endif /* __STORAGE_TEST_H__ */