diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-10 17:09:24 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-12 18:50:47 +0200 |
| commit | 660c67a01f93817efebf312c5f6d685e8329312e (patch) | |
| tree | dbcc8d8c6aee76be9906817d641410d72aa323ef /src/soc/intel/quark/include | |
| parent | 89186b2eb8167b56bf76d9cc03587d678b9bc661 (diff) | |
soc/intel/quark: Add host bridge access support
Add host bridge register access routines and macros.
TEST=Build and run on Galileo Gen2
Change-Id: I52eb6a68e99533fbb69c0ae1e6d581e4c4fab9d2
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15593
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/reg_access.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index b934032358..8a1833349e 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -36,6 +36,7 @@ enum { PCIE_AFE_REGS, PCIE_RESET, GPE0_REGS, + HOST_BRIDGE, }; enum { @@ -89,6 +90,27 @@ enum { #define REG_GPIO_XOR(reg_, value_) \ REG_GPIO_RXW(reg_, 0xffffffff, value_) +/* Host bridge register access macros */ +#define REG_HOST_BRIDGE_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + HOST_BRIDGE) +#define REG_HOST_BRIDGE_READ(reg_) \ + REG_HOST_BRIDGE_ACCESS(READ, reg_, 0, 0, 0) +#define REG_HOST_BRIDGE_WRITE(reg_, value_) \ + REG_HOST_BRIDGE_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_HOST_BRIDGE_AND(reg_, value_) \ + REG_HOST_BRIDGE_RMW(reg_, value_, 0) +#define REG_HOST_BRIDGE_RMW(reg_, mask_, value_) \ + REG_HOST_BRIDGE_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_HOST_BRIDGE_RXW(reg_, mask_, value_) \ + REG_HOST_BRIDGE_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_HOST_BRIDGE_OR(reg_, value_) \ + REG_HOST_BRIDGE_RMW(reg_, 0xffffffff, value_) +#define REG_HOST_BRIDGE_POLL(reg_, mask_, value_, timeout_) \ + REG_HOST_BRIDGE_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_HOST_BRIDGE_XOR(reg_, value_) \ + REG_HOST_BRIDGE_RXW(reg_, 0xffffffff, value_) + /* Legacy GPIO register access macros */ #define REG_LEG_GPIO_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ @@ -208,6 +230,7 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t reg_host_bridge_unit_read(uint32_t reg_address); uint32_t reg_legacy_gpio_read(uint32_t reg_address); void reg_legacy_gpio_write(uint32_t reg_address, uint32_t value); uint32_t reg_rmu_temp_read(uint32_t reg_address); |