diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-30 18:21:53 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-03 18:03:46 +0200 |
| commit | 5fafc6ad540c12776d2cafa5bef0f5fca5b1e977 (patch) | |
| tree | e957649af477d5c9584655cbbcde650953e0a89f /src/soc/intel/quark/include | |
| parent | 72fe7acbbb9ef81a30950accbc241e31fc772893 (diff) | |
soc/intel/quark: Support access to CPU CR registers
Add support to access CR0 and CR4.
TEST=Build and run on Galileo Gen2.
Change-Id: I8084b7824ae9fbcd55e11a7b5eec142591a7e279
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/16004
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/include')
| -rw-r--r-- | src/soc/intel/quark/include/soc/reg_access.h | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/intel/quark/include/soc/reg_access.h b/src/soc/intel/quark/include/soc/reg_access.h index 0e64917177..8be7f83e88 100644 --- a/src/soc/intel/quark/include/soc/reg_access.h +++ b/src/soc/intel/quark/include/soc/reg_access.h @@ -19,6 +19,7 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <cpu/x86/cr.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <delay.h> @@ -39,6 +40,7 @@ enum { PCIE_RESET, GPE0_REGS, HOST_BRIDGE, + CPU_CR, }; enum { @@ -50,6 +52,27 @@ enum { _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_, SOC_TYPE, \ size_, reg_, mask_, value_, timeout_, reg_set_) +/* CPU CRx register access macros */ +#define REG_CPU_CR_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ + SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ + CPU_CR) +#define REG_CPU_CR_READ(reg_) \ + REG_CPU_CR_ACCESS(READ, reg_, 0, 0, 0) +#define REG_CPU_CR_WRITE(reg_, value_) \ + REG_CPU_CR_ACCESS(WRITE, reg_, 0, value_, 0) +#define REG_CPU_CR_AND(reg_, value_) \ + REG_CPU_CR_RMW(reg_, value_, 0) +#define REG_CPU_CR_RMW(reg_, mask_, value_) \ + REG_CPU_CR_ACCESS(RMW, reg_, mask_, value_, 0) +#define REG_CPU_CR_RXW(reg_, mask_, value_) \ + REG_CPU_CR_ACCESS(RXW, reg_, mask_, value_, 0) +#define REG_CPU_CR_OR(reg_, value_) \ + REG_CPU_CR_RMW(reg_, 0xffffffff, value_) +#define REG_CPU_CR_POLL(reg_, mask_, value_, timeout_) \ + REG_CPU_CR_ACCESS(POLL, reg_, mask_, value_, timeout_) +#define REG_CPU_CR_XOR(reg_, value_) \ + REG_CPU_CR_RXW(reg_, 0xffffffff, value_) + /* GPE0 controller register access macros */ #define REG_GPE0_ACCESS(cmd_, reg_, mask_, value_, timeout_) \ SOC_ACCESS(cmd_, reg_, REG_SCRIPT_SIZE_32, mask_, value_, timeout_, \ |