diff options
| author | Lijian Zhao <lijian.zhao@intel.com> | 2017-12-01 12:53:43 -0800 |
|---|---|---|
| committer | Aaron Durbin <adurbin@chromium.org> | 2017-12-11 19:29:15 +0000 |
| commit | 408d76f8673ec69ae8b48ad93e0889d46652c322 (patch) | |
| tree | fe0b492a448318c74cb946055c9ba19c1e4ffdc2 /src/soc/intel/quark/i2c.c | |
| parent | 5598db254fe34cb9b3557fcfba915d90725bf173 (diff) | |
soc/intel/cannonlake: Add support for D0 stepping
D0 stepping with CPUID 0x60663 need to be added in coreboot.
TEST=Boot up with D0 stepping processor
Change-Id: I3b0f2616843367d2bfbee1b5bf75772b9e83e931
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/22676
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/i2c.c')
0 files changed, 0 insertions, 0 deletions