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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-08 07:12:30 -0800 |
|---|---|---|
| committer | Stefan Reinauer <stefan.reinauer@coreboot.org> | 2016-02-10 03:12:10 +0100 |
| commit | d4edacb2e4803bd06091e3c57a1f087388228529 (patch) | |
| tree | 29aeb2cd667de9cd9c5dcdbd57135bec0e80ff5b /src/soc/intel/quark/Makefile.inc | |
| parent | 43cdff6b453e0563414a020c2bab69a841a8f2e8 (diff) | |
soc/intel/quark: Call FSP SiliconInit
Optionally relocate FSP into DRAM and then call FSP SiliconInit.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Add "select DISPLAY_FSP_ENTRY_POINTS"
* Add "select DISPLAY_HOBS"
* Optionally add "select RELOCATE_FSP_INTO_DRAM"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* FSP entry points are displayed and
* The message "FspSiliconInit returned 0x00000000" is displayed and
* The HOBs are displayed correctly and
* The message "ERROR - Missing one or more required FSP HOBs!" is
not displayed
Change-Id: I91e660ea373a8bb00fc97fe8b760347cbfa96b1e
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13631
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 915360a635..e5594bee95 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -22,10 +22,12 @@ romstage-y += memmap.c romstage-y += tsc_freq.c romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c +ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c +CPPFLAGS_common += -I$(src)/soc/intel/quark CPPFLAGS_common += -I$(src)/soc/intel/quark/include # Chipset microcode path |