diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-07-20 08:58:58 -0700 |
|---|---|---|
| committer | Lee Leahy <leroy.p.leahy@intel.com> | 2016-08-03 17:47:53 +0200 |
| commit | 01728bb2ed1847dadf1429fafe0be2cb7876eed8 (patch) | |
| tree | dac9a0682b205409038d4b742350ba28e2dc1af3 /src/soc/intel/quark/Makefile.inc | |
| parent | 3d0e3cf4b125dfda236d6978adea5f5d40fd78e8 (diff) | |
soc/intel/quark: Prepare for FSP2.0 support
Split the original contents of romstage.c into car.c, romstage.c and
fsp1_1.c.
TEST=Build and run on Galileo Gen2
Change-Id: I6392d7382e383ea2087afa6bf45b1f087ba78d79
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15862
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index f5b9746159..4740ec77a7 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -34,6 +34,7 @@ romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += ehci.c +ramstage-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1.c ramstage-y += gpio_i2c.c ramstage-y += i2c.c ramstage-y += lpc.c |