soc/intel/quark: Add FSP 2.0 romstage support

Add the pieces necessary to successfully build and run romstage using
the FSP 2.0 build.  Because romstage is using postcar, add the postcar
pieces so that romstage can attempt to load postcar.

TEST=Build and run on Galileo Gen2

Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15866
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc
index a6454d9a1c..bd297ed8d7 100644
--- a/src/soc/intel/quark/Makefile.inc
+++ b/src/soc/intel/quark/Makefile.inc
@@ -30,6 +30,14 @@ romstage-y += memmap.c
 romstage-y += reg_access.c
 romstage-y += tsc_freq.c
 romstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
+romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c
+
+postcar-y += fsp2_0.c
+postcar-y += i2c.c
+postcar-y += memmap.c
+postcar-y += reg_access.c
+postcar-y += tsc_freq.c
+postcar-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c
 
 ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c
 ramstage-y += chip.c
@@ -54,6 +62,9 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include/soc/fsp
 # Chipset microcode path
 CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark
 
+# Since FSP-M runs in CAR we need to relocate it to a specific address
+$(CONFIG_FSP_M_CBFS)-options := -b $(CONFIG_FSP_ESRAM_LOC)
+
 # Add the FSP binary to the CBFS image
 cbfs-files-$(CONFIG_ADD_FSP_RAW_BIN) += fsp.bin
 fsp.bin-file := $(call strip_quotes,$(CONFIG_FSP_FILE))