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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-02 07:17:06 -0800 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-02-08 20:15:05 +0100 |
| commit | 9fd0895cb4a8cf8d4ece09d62628b6d4b91177ae (patch) | |
| tree | 2337f3f48f7c4dce491edb04a7530e6749f83fda /src/soc/intel/quark/Makefile.inc | |
| parent | cff5f09e9340229cade13960f1c08ede7ec5596f (diff) | |
soc/intel/quark: Enable ESRAM
The Quark SoC uses ESRAM instead of cache-as-RAM. This code requires
that utils/xcompile/xcompile change the machine architecture from i686
to i586 to ensure that the Quark does not attempt to execute unsupported
instructions:
* Adjust Makefile.inc to add the RMU to the coreboot image
* Add code to enable the ESRAM
Directly use the QuarkSocPkg/QuarkNorthCluster/Include/QuarkNcSocId.h
file from the EDK2 tree (https://github.com/tianocore/edk2.git) to
enable
easy differences and correct issues in coreboot that were found in EDK2.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_RMU_FILE"
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Remove power from the board
* Apply power to the board
* Testing is successful if the SD LED is on indicating that the end of
esram_init.inc was reached
Change-Id: I91d919da144bb72a5d4c4a8050ffab256632a395
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13440
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/Makefile.inc')
| -rw-r--r-- | src/soc/intel/quark/Makefile.inc | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index 6327ae6548..8e24d9b44f 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -15,6 +15,7 @@ ifeq ($(CONFIG_SOC_INTEL_QUARK),y) +subdirs-y += romstage subdirs-y += ../../../cpu/x86/tsc romstage-y += memmap.c @@ -26,4 +27,10 @@ CPPFLAGS_common += -I$(src)/soc/intel/quark/include # Chipset microcode path CPPFLAGS_common += -I3rdparty/blobs/soc/intel/quark +# Add the chipset microcode file to the CBFS image +cbfs-files-$(CONFIG_ADD_RMU_FILE) += rmu.bin +rmu.bin-file := $(call strip_quotes,$(CONFIG_RMU_FILE)) +rmu.bin-position := $(CONFIG_RMU_LOC) +rmu.bin-type := raw + endif # CONFIG_SOC_INTEL_QUARK |