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authorSubrata Banik <subratabanik@google.com>2022-02-10 12:38:02 +0530
committerFelix Held <felix-coreboot@felixheld.de>2022-02-18 20:21:45 +0000
commit34f26b298961300fe97234ac5f424f57ebd04aad (patch)
tree9221a4e220dfacee5ecda62ee216104416933e74 /src/soc/intel/quark/Kconfig
parent03c0853f4d58c73a632f81cac2eb16b759d7f338 (diff)
drivers/fsp/fsp2_0: Rework FSP Notify Phase API configs
This patch renames all FSP Notify Phase API configs to primarily remove "SKIP_" prefix. 1. SKIP_FSP_NOTIFY_PHASE_AFTER_PCI_ENUM -> USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM 2. SKIP_FSP_NOTIFY_PHASE_READY_TO_BOOT -> USE_FSP_NOTIFY_PHASE_READY_TO_BOOT 3. SKIP_FSP_NOTIFY_PHASE_END_OF_FIRMWARE -> USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE The idea here is to let SoC selects all required FSP configs to execute FSP Notify Phase APIs unless SoC deselects those configs to run native coreboot implementation as part of the `.final` ops. For now all SoC that uses FSP APIs have selected all required configs to let FSP to execute Notify Phase APIs. Note: coreboot native implementation to skip FSP notify phase API (post pci enumeration) is still WIP. Additionally, fixed SoC configs inclusion order alphabetically.  BUG=b:211954778 TEST=Able to build and boot brya. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib95368872acfa3c49dad4eb7d0d73fca04b4a1fb Reviewed-on: https://review.coreboot.org/c/coreboot/+/61792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Diffstat (limited to 'src/soc/intel/quark/Kconfig')
-rw-r--r--src/soc/intel/quark/Kconfig5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig
index ad885d5f6d..2ecdd37a15 100644
--- a/src/soc/intel/quark/Kconfig
+++ b/src/soc/intel/quark/Kconfig
@@ -11,6 +11,7 @@ config CPU_SPECIFIC_OPTIONS
def_bool y
select ARCH_X86
select NO_ECAM_MMCONF_SUPPORT
+ select NO_SMM
select REG_SCRIPT
select PLATFORM_USES_FSP2_0
select SOC_INTEL_COMMON
@@ -21,8 +22,10 @@ config CPU_SPECIFIC_OPTIONS
select UDELAY_TSC
select TSC_MONOTONIC_TIMER
select UNCOMPRESSED_RAMSTAGE
+ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM
+ select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT
+ select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE
select USE_MARCH_586
- select NO_SMM
#####
# Debug serial output