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| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-06-05 18:48:31 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2016-06-12 14:52:44 +0200 |
| commit | ce9e21a0ea78039d80838071f9514c6a2ddaa8bc (patch) | |
| tree | a32c69c26338c0cea22e04628fb4b96465648744 /src/soc/intel/quark/Kconfig | |
| parent | 6c3c31e49d6b53d549de5c815ed9a2f7ab5a3521 (diff) | |
soc/intel/quark: Add C bootblock
Add a bootblock which builds with C_ENVIRONMENT_BOOTBLOCK selected.
This is the first piece in supporting FSP 2.0. Move esraminit from
romstage into the bootblock. Replace cache_as_ram with
car_stage_entry.S and code in romstage.c
TEST=Build and run on Galileo Gen2
Change-Id: I14d2af2adb6e75d4bff1ebfb863196df04d07daf
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/15132
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Diffstat (limited to 'src/soc/intel/quark/Kconfig')
| -rw-r--r-- | src/soc/intel/quark/Kconfig | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 2c7ec641b6..37b669d828 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,6 +26,8 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select BOOTBLOCK_SAVE_BIST_AND_TIMESTAMP + select C_ENVIRONMENT_BOOTBLOCK select REG_SCRIPT select SOC_INTEL_COMMON select SOC_SETS_MTRRS @@ -261,4 +263,17 @@ config RMU_LOC The location in CBFS that the RMU is located. It must match the strap-determined base address. +##### +# Bootblock +# The following options support the C_ENVIRONMENT_BOOTBLOCK. +##### + +config DCACHE_BSP_STACK_SIZE + hex + default 0x4000 + +config C_ENV_BOOTBLOCK_SIZE + hex + default 0x8000 + endif # SOC_INTEL_QUARK |