diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2016-02-07 14:37:13 -0800 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-02-09 16:20:38 +0100 |
| commit | 87df8d08d676f79b894da84ebe6f8a57f69ba5b1 (patch) | |
| tree | c631ba642e44184808868342efd8055ec30731aa /src/soc/intel/quark/Kconfig | |
| parent | 5d7df71cfe6c5a4c8615f33d194cb34947f53c05 (diff) | |
soc/intel/quark: Enable Serial Port
Add the code to enable debug serial output using HSUART1:
* Enable the code using Kconfig value ENABLE_BUILTIN_HSUART1
* Note that the BIST value is always zero as validated in
esram_init.inc
* The initial TSC value is currently not saved!
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if serial output is present on HSUART1 at
115200 baud, 8-bit, no parity
Change-Id: I7e6181e8b9bc901c3ab236f0b56534850bb6bfd0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13445
Tested-by: build bot (Jenkins)
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Diffstat (limited to 'src/soc/intel/quark/Kconfig')
| -rw-r--r-- | src/soc/intel/quark/Kconfig | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index 802f972058..d99cd54156 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -26,9 +26,38 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select ARCH_ROMSTAGE_X86_32 select ARCH_VERSTAGE_X86_32 + select SOC_INTEL_COMMON + select TSC_CONSTANT_RATE + select UDELAY_TSC select USE_MARCH_586 ##### +# Debug serial output +# The following options configure the debug serial port +##### + +config ENABLE_BUILTIN_HSUART1 + bool "Enable built-in HSUART1" + default y + select NO_UART_ON_SUPERIO + select DRIVERS_UART_8250MEM_32 + help + The Quark SoC has two HSUART. Choose this option to configure the pads + and enable HSUART1, which can be used for the debug console. + +config TTYS0_BASE + hex "HSUART1 Base Address" + depends on ENABLE_BUILTIN_HSUART1 + default 0xA0019000 + help + Memory mapped MMIO of HSUART1. + +config TTYS0_LCS + int + depends on ENABLE_BUILTIN_HSUART1 + default 3 + +##### # Debug support # The following options provide debug support for the Quark coreboot # code. The SD LED is used as a binary marker to determine if a @@ -65,6 +94,19 @@ config ENABLE_DEBUG_LED_TEMPRAMINIT Indicate that TempRamInit was successful. ##### +# ESRAM layout +# Specify the portion of the ESRAM for coreboot to use as its data area. +##### + +config DCACHE_RAM_BASE + hex + default 0x80070000 + +config DCACHE_RAM_SIZE + hex + default 0x00008000 + +##### # Flash layout # Specify the size of the coreboot file system in the read-only # (recovery) portion of the flash part. |