diff options
| author | Subrata Banik <subratabanik@google.com> | 2024-11-19 17:34:56 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-20 03:55:00 +0000 |
| commit | d22078a3c3b090a0d0c900520dc10dd8f09cda5c (patch) | |
| tree | 6715075f57c6e2a7775e2b36dbd5e2cd102a7002 /src/soc/intel/pantherlake | |
| parent | 1b86f5ca9a02a2f2d2d799def68698b15feaa676 (diff) | |
soc/intel/pantherlake: Enable CPU feature programming in coreboot
This patch enables coreboot to perform CPU feature programming for both
the Boot Strap Processor (BSP) and Application Processors (APs) on
Intel Panther Lake platforms.
This change eliminates the need for the following FSP modules:
- CpuMpPpi
- CpuFeature
By handling CPU feature programming within coreboot, we reduce reliance
on external FSP binaries and improve code maintainability.
BUG=b:376092389, b/364822529
TEST=Built and booted google/fatcat successfully. Verified CPU features
are correctly programmed.
Change-Id: I73321485327f6a02ec8338fcfa1faf1e71008ba6
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/soc/intel/pantherlake')
| -rw-r--r-- | src/soc/intel/pantherlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/pantherlake/cpu.c | 13 |
2 files changed, 13 insertions, 1 deletions
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 96324b7c09..4098757490 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -368,6 +368,7 @@ config SOC_INTEL_GFX_FRAMEBUFFER_OFFSET config DROP_CPU_FEATURE_PROGRAM_IN_FSP bool + default y if MP_SERVICES_PPI_V2_NOOP || CHROMEOS default n help This is to avoid FSP running basic CPU feature programming on BSP diff --git a/src/soc/intel/pantherlake/cpu.c b/src/soc/intel/pantherlake/cpu.c index 659ba0cf12..28fa1d890f 100644 --- a/src/soc/intel/pantherlake/cpu.c +++ b/src/soc/intel/pantherlake/cpu.c @@ -138,7 +138,18 @@ void soc_core_init(struct device *cpu) if (CONFIG(INTEL_TME) && is_tme_supported()) set_tme_core_activate(); - /* TODO: Add support for DROP_CPU_FEATURE_PROGRAM_IN_FSP */ + if (CONFIG(DROP_CPU_FEATURE_PROGRAM_IN_FSP)) { + /* Disable 3-strike error */ + disable_signaling_three_strike_event(); + + set_aesni_lock(); + + /* Enable VMX */ + set_feature_ctrl_vmx_arg(CONFIG(ENABLE_VMX) && !conf->disable_vmx); + + /* Feature control lock configure */ + set_feature_ctrl_lock(); + } } static void per_cpu_smm_trigger(void) |