diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2024-11-12 10:27:53 -0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-18 02:54:25 +0000 |
| commit | 38fd03dfea97b78e100a30862d41b1d775d0b526 (patch) | |
| tree | a2aa1c9f6c8c06f2ec8470aac2917955196e7c2d /src/soc/intel/pantherlake | |
| parent | a9e5ab7bb00ec2363abea4e44baf98a8130fbb2e (diff) | |
soc/intel/pantherlake: Bind SoC config to LowerBasicMemTestSize UPD
The lower_basic_mem_test_size SoC setting (LowerBasicMemTestSize UPD)
request FSP-M to reduce the size of memory tested after memory
training. This option reduces the boot time. This is considered a safe
option to enable on a well validated board.
BUG=b:357011633
TEST=LowerBasicMemTestSize UPD is set when lower_basic_mem_test_size
is set
Change-Id: I465e9c138ac8f2079bfd506add4667201a8fa533
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85130
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/pantherlake')
| -rw-r--r-- | src/soc/intel/pantherlake/romstage/fsp_params.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index e6ed19ec85..83481a01f4 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -79,6 +79,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->RMT = config->rmt; m_cfg->MrcFastBoot = 1; + m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; } static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, |