soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
	Panther Lake U/H 12Xe/H 4Xe External Design
	Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
	Volume 2 of 2 #813030

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

7 files changed, 395 insertions, 0 deletions

diff --git a/src/soc/intel/pantherlake/include/soc/gpe.h b/src/soc/intel/pantherlake/include/soc/gpe.h
new file mode 100644
index 0000000000..eb9a8bff85
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/gpe.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_GPE_H_
+#define _SOC_PANTHERLAKE_GPE_H_
+
+#include <intelpch/gpe.h>
+
+#endif /* _SOC_PANTHERLAKE_GPE_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/meminit.h b/src/soc/intel/pantherlake/include/soc/meminit.h
new file mode 100644
index 0000000000..78c509b519
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/meminit.h
@@ -0,0 +1,104 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_MEMINIT_H_
+#define _SOC_PANTHERLAKE_MEMINIT_H_
+
+#include <fsp/soc_binding.h>
+#include <intelblocks/meminit.h>
+#include <types.h>
+
+enum mem_type {
+	MEM_TYPE_LP5X,
+};
+
+struct lpx_dq {
+	uint8_t dq0[BITS_PER_BYTE];
+	uint8_t dq1[BITS_PER_BYTE];
+};
+
+struct lpx_dqs {
+	uint8_t dqs0;
+	uint8_t dqs1;
+};
+
+struct lpx_dq_map {
+	struct lpx_dq ddr0;
+	struct lpx_dq ddr1;
+	struct lpx_dq ddr2;
+	struct lpx_dq ddr3;
+	struct lpx_dq ddr4;
+	struct lpx_dq ddr5;
+	struct lpx_dq ddr6;
+	struct lpx_dq ddr7;
+};
+
+struct lpx_dqs_map {
+	struct lpx_dqs ddr0;
+	struct lpx_dqs ddr1;
+	struct lpx_dqs ddr2;
+	struct lpx_dqs ddr3;
+	struct lpx_dqs ddr4;
+	struct lpx_dqs ddr5;
+	struct lpx_dqs ddr6;
+	struct lpx_dqs ddr7;
+};
+
+struct mem_lp5x_config {
+	uint8_t ccc_config;
+};
+
+struct rcomp {
+	/*
+	 * Rcomp resistor value. This values represents the resistance in
+	 * ohms of the rcomp resistor attached to the DDR_COMP pin on the SoC.
+	 *
+	 * Note: If mainboard users don't want to override rcomp related settings
+	 * then associated rcomp UPDs will have its default value.
+	 */
+	uint16_t resistor;
+	/* Rcomp target values. */
+	uint16_t targets[5];
+};
+
+struct mb_cfg {
+	enum mem_type type;
+	struct rcomp rcomp;
+	union {
+		/*
+		 * DQ CPU<>DRAM map:
+		 * Index of the array represents DQ# on the CPU and the value represents DQ# on
+		 * the DRAM part.
+		 */
+		uint8_t dq_map[CONFIG_DATA_BUS_WIDTH];
+		struct lpx_dq_map lpx_dq_map;
+	};
+
+	union {
+		/*
+		 * DQS CPU<>DRAM map:
+		 * Index of the array represents DQS# on the CPU and the value represents DQS#
+		 * on the DRAM part.
+		 */
+		uint8_t dqs_map[CONFIG_DATA_BUS_WIDTH/BITS_PER_BYTE];
+		struct lpx_dqs_map lpx_dqs_map;
+	};
+
+	struct mem_lp5x_config lp5x_config;
+
+	/* Early Command Training Enable/Disable Control */
+	bool ect;
+
+	/* Board type */
+	uint8_t user_bd;
+
+	/* Command Mirror */
+	uint8_t cmd_mirror;
+
+	/* Enable/Disable TxDqDqs Retraining for LP5 */
+	uint8_t lp_ddr_dq_dqs_re_training;
+};
+
+void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
+		 const struct mem_spd *spd_info, bool half_populated);
+
+#endif /* _SOC_PANTHERLAKE_MEMINIT_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/msr.h b/src/soc/intel/pantherlake/include/soc/msr.h
new file mode 100644
index 0000000000..a268cd2af6
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/msr.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_MSR_H_
+#define _SOC_PANTHERLAKE_MSR_H_
+
+#include <intelblocks/msr.h>
+
+#define MSR_BIOS_DONE		        0x151
+#define   ENABLE_IA_UNTRUSTED	        BIT(0)
+
+#endif /* _SOC_PANTHERLAKE_MSR_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/pmc.h b/src/soc/intel/pantherlake/include/soc/pmc.h
new file mode 100644
index 0000000000..daa60f2080
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/pmc.h
@@ -0,0 +1,174 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_PMC_H_
+#define _SOC_PANTHERLAKE_PMC_H_
+#include <device/device.h>
+
+extern struct device_operations pmc_ops;
+
+/* PCI Configuration Space (D31:F2): PMC */
+#define  PWRMBASE		0x10
+#define  ABASE			0x20
+
+/* General PM Configuration A */
+#define GEN_PMCON_A			0x1020
+#define   DC_PP_DIS			BIT(30)
+#define   DSX_PP_DIS			BIT(29)
+#define   AG3_PP_EN			BIT(28)
+#define   SX_PP_EN			BIT(27)
+#define   ALLOW_ICLK_PLL_SD_INC0	BIT(26)
+#define   GBL_RST_STS			BIT(24)
+#define   DISB				BIT(23)
+#define   ALLOW_OPI_PLL_SD_INC0		BIT(22)
+#define   MEM_SR			BIT(21)
+#define   ALLOW_SPXB_CG_INC0		BIT(20)
+#define   ALLOW_L1LOW_C0		BIT(19)
+#define   MS4V				BIT(18)
+#define   ALLOW_L1LOW_OPI_ON		BIT(17)
+#define   SUS_PWR_FLR			BIT(16)
+#define   PME_B0_S5_DIS			BIT(15)
+#define   PWR_FLR			BIT(14)
+#define   ALLOW_L1LOW_BCLKREQ_ON	BIT(13)
+#define   DIS_SLP_X_STRCH_SUS_UP	BIT(12)
+#define   SLP_S3_MIN_ASST_WDTH_MASK	(3 << 10)
+#define     SLP_S3_MIN_ASST_WDTH_60USEC	(0 << 10)
+#define     SLP_S3_MIN_ASST_WDTH_1MS	BIT(10)
+#define     SLP_S3_MIN_ASST_WDTH_50MS	(2 << 10)
+#define     SLP_S3_MIN_ASST_WDTH_2S	(3 << 10)
+#define   HOST_RST_STS			BIT(9)
+#define   ESPI_SMI_LOCK			BIT(8)
+#define   S4MAW_MASK			(3 << 4)
+#define     S4MAW_1S			BIT(4)
+#define     S4MAW_2S			(2 << 4)
+#define     S4MAW_3S			(3 << 4)
+#define     S4MAW_4S			(0 << 4)
+#define     S4ASE			BIT(3)
+#define   PER_SMI_SEL_MASK		(3 << 1)
+#define     SMI_RATE_64S		(0 << 1)
+#define     SMI_RATE_32S		BIT(1)
+#define     SMI_RATE_16S		(2 << 1)
+#define     SMI_RATE_8S			(3 << 1)
+#define   SLEEP_AFTER_POWER_FAIL	BIT(0)
+
+/* General PM Configuration B */
+#define GEN_PMCON_B			0x1024
+#define   ST_FDIS_LOCK			BIT(21)
+#define   SLP_STR_POL_LOCK		BIT(18)
+#define   ACPI_BASE_LOCK		BIT(17)
+#define   PM_DATA_BAR_DIS		BIT(16)
+#define   WOL_EN_OVRD			BIT(13)
+#define   BIOS_PCI_EXP_EN		BIT(10)
+#define   PWRBTN_LVL			BIT(9)
+#define   SMI_LOCK			BIT(4)
+#define   RTC_BATTERY_DEAD		BIT(2)
+
+/* Extended Test Mode Register */
+#define ETR				0x1048
+#define   CF9_LOCK			BIT(31)
+#define   CF9_GLB_RST			BIT(20)
+
+/* Set strap message lock */
+#define SSML				0x104C
+#define   SSML_SSL_DS			(0 << 0)
+#define   SSML_SSL_EN			BIT(0)
+
+/* Set strap msg control */
+#define SSMC				0x1050
+#define   SSMC_SSMS			BIT(0)
+
+/* Set strap message data */
+#define SSMD				0x1054
+#define   SSMD_SSD_MASK			(0xffff << 0)
+
+/* Power and Reset Status */
+#define PRSTS				0x1810
+
+/* Power Management Configuration */
+#define PM_CFG				0x1818
+#define   PM_CFG_DBG_MODE_LOCK		BIT(27)
+#define   PM_CFG_XRAM_READ_DISABLE	BIT(22)
+
+/* S3 Power Gating Policies */
+#define S3_PWRGATE_POL			0x1828
+#define   S3DC_GATE_SUS			BIT(1)
+#define   S3AC_GATE_SUS			BIT(0)
+
+/* S4 power gating policies */
+#define S4_PWRGATE_POL			0x182c
+#define   S4DC_GATE_SUS			BIT(1)
+#define   S4AC_GATE_SUS			BIT(0)
+
+/* S5 power gating policies */
+#define S5_PWRGATE_POL			0x1830
+#define   S5DC_GATE_SUS			BIT(15)
+#define   S5AC_GATE_SUS			BIT(14)
+
+/* Deep Sx configuration */
+#define DSX_CFG				0x1834
+#define   REQ_CNV_NOWAKE_DSX		BIT(4)
+#define   REQ_BATLOW_DSX		BIT(3)
+#define   DSX_EN_WAKE_PIN		BIT(2)
+#define   DSX_DIS_AC_PRESENT_PD	BIT(1)
+#define   DSX_EN_LAN_WAKE_PIN		BIT(0)
+#define DSX_CFG_MASK			(0x1f << 0)
+
+#define PMSYNC_TPR_CFG			0x18C4
+#define   PCH2CPU_TPR_CFG_LOCK		BIT(31)
+#define   PCH2CPU_TT_EN			BIT(26)
+
+/* ACPI Timer Control */
+#define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define   ACPI_TIM_DIS			BIT(1)
+#define GPIO_GPE_CFG			0x1920
+#define   GPE0_DWX_MASK			0xf
+#define   GPE0_DW_SHIFT(x)		(4*(x))
+
+/* GPIO community groups */
+#define PMC_GPP_V		0x0
+#define PMC_GPP_C		0x1
+#define PMC_GPP_F		0x2
+#define PMC_GPP_E		0x3
+#define PMC_GPP_A		0x4
+#define PMC_GPP_H		0x5
+#define PMC_GPP_VGPIO		0x6
+#define PMC_GPP_B		0x7
+#define PMC_GPP_D		0x8
+#define PMC_GPP_S		0x9
+
+/* Global reset causes 0 */
+#define GBLRST_CAUSE0			0x1924
+#define   GBLRST_CAUSE0_THERMTRIP	BIT(5)
+
+/* Global reset causes 1 */
+#define GBLRST_CAUSE1			0x1928
+
+/* Host partition reset causes */
+#define HPR_CAUSE0			0x192C
+#define   HPR_CAUSE0_MI_HRPD		BIT(10)
+#define   HPR_CAUSE0_MI_HRPC		BIT(9)
+#define   HPR_CAUSE0_MI_HR		BIT(8)
+
+/* Sleep S0 residency */
+#define SLP_S0_RES			0x193c
+
+#define CPPMVRIC			0x1B1C
+#define   XTALSDQDIS			BIT(22)
+
+#define IRQ_REG				ACTL
+#define SCI_IRQ_ADJUST			0
+
+/* ACPI Control */
+#define ACTL				0x1BD8
+#define   PWRM_EN			BIT(8)
+#define   ACPI_EN			BIT(7)
+#define   SCI_IRQ_SEL			(7 << 0)
+
+#define  SCIS_IRQ9			0
+#define  SCIS_IRQ10			1
+#define  SCIS_IRQ11			2
+#define  SCIS_IRQ20			4
+#define  SCIS_IRQ21			5
+#define  SCIS_IRQ22			6
+#define  SCIS_IRQ23			7
+
+#endif /* _SOC_PANTHERLAKE_PMC_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/romstage.h b/src/soc/intel/pantherlake/include/soc/romstage.h
new file mode 100644
index 0000000000..733a11b7aa
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/romstage.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_ROMSTAGE_H_
+#define _SOC_PANTHERLAKE_ROMSTAGE_H_
+
+#include <fsp/api.h>
+#include <soc/soc_chip.h>
+
+void mainboard_memory_init_params(FSPM_UPD *memupd);
+void systemagent_early_init(void);
+
+/* Board type */
+enum board_type {
+	BOARD_TYPE_MOBILE  = 0,
+	BOARD_TYPE_DESKTOP = 1,
+	BOARD_TYPE_ULT_ULX = 5,
+	BOARD_TYPE_SERVER  = 7
+};
+
+#endif /* _SOC_PANTHERLAKE_ROMSTAGE_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/soc_chip.h b/src/soc/intel/pantherlake/include/soc/soc_chip.h
new file mode 100644
index 0000000000..a1d064b5bb
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/soc_chip.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_SOC_CHIP_H_
+#define _SOC_PANTHERLAKE_SOC_CHIP_H_
+
+#include "../../chip.h"
+
+#endif /* _SOC_PANTHERLAKE_SOC_CHIP_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/systemagent.h b/src/soc/intel/pantherlake/include/soc/systemagent.h
new file mode 100644
index 0000000000..c791e5bbe8
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/systemagent.h
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_SYSTEMAGENT_H_
+#define _SOC_PANTHERLAKE_SYSTEMAGENT_H_
+
+#include <intelblocks/systemagent.h>
+
+/* Device 0:0.0 PCI configuration space */
+
+#define SAFBAR		0x68
+#define EPBAR		0x40
+#define CAPID0_A	0xe4
+#define  VTD_DISABLE	(1 << 23)
+
+/* MCHBAR offsets */
+#define VTDBAR			0x5410
+#define GFXVTBAR		VTDBAR
+#define REGBAR			0x5420
+#define MCH_DDR_POWER_LIMIT_LO	0x58e0
+#define MCH_DDR_POWER_LIMIT_HI	0x58e4
+#define MCH_PKG_POWER_LIMIT_LO	0x59a0
+#define MCH_PKG_POWER_LIMIT_HI	0x59a4
+#define BIOS_RESET_CPL		0x5da8
+#define IMRBASE			0x6a40
+#define IMRLIMIT		0x6a48
+#define IPUVTBAR		0x7880
+#define TBTxBAR(x)		(0x7888 + (x) * 8)
+
+#define MAX_TBT_PCIE_PORT	4
+
+#define VTBAR_ENABLED		0x01
+#define VTBAR_MASK		0x7ffffff000ull
+
+static const struct sa_mmio_descriptor soc_vtd_resources[] = {
+	{ VTDBAR, VTD_BASE_ADDRESS, VTD_BASE_SIZE, "VTDBAR" },
+};
+
+#define V_P2SB_CFG_IBDF_BUS	0
+#define V_P2SB_CFG_IBDF_DEV	30
+#define V_P2SB_CFG_IBDF_FUNC	7
+#define V_P2SB_CFG_HBDF_BUS	0
+#define V_P2SB_CFG_HBDF_DEV	30
+#define V_P2SB_CFG_HBDF_FUNC	6
+
+#define CRAB_ABORT_BASE_ADDR	0xFEB00000
+#define CRAB_ABORT_SIZE		(512 * KiB)
+#define TPM_BASE_ADDRESS	0xFED40000
+#define TPM_SIZE		(64 * KiB)
+#define LT_SECURITY_BASE_ADDR	0xFED20000
+#define LT_SECURITY_SIZE	(384 * KiB)
+#define APIC_SIZE		(1 * MiB)
+
+#define MASK_PCIEXBAR_LENGTH	0x0000000E // bits [3:1]
+#define PCIEXBAR_LENGTH_LSB	1 // used to shift right
+
+#define  DSM_BASE_ADDR_REG	0xB0
+#define  MASK_DSM_LENGTH	0xFF00 // [15:8]
+#define  MASK_DSM_LENGTH_LSB	8 // used to shift right
+#define  MASK_GSM_LENGTH	0xC0 // [7:6]
+#define  MASK_GSM_LENGTH_LSB	6 // used to shift right
+#define  DPR_REG		0x5C
+#define  MASK_DPR_LENGTH	0xFF0 // [11:4]
+#define  MASK_DPR_LENGTH_LSB	4 // used to shift right
+
+uint64_t get_mmcfg_size(const struct device *dev);
+uint64_t get_dsm_size(const struct device *dev);
+uint64_t get_gsm_size(const struct device *dev);
+uint64_t get_dpr_size(const struct device *dev);
+
+#endif /* _SOC_PANTHERLAKE_SYSTEMAGENT_H_ */