soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

14 files changed, 345 insertions, 16 deletions

diff --git a/src/soc/intel/pantherlake/include/soc/cpu.h b/src/soc/intel/pantherlake/include/soc/cpu.h
new file mode 100644
index 0000000000..2ca9a1043c
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/cpu.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_CPU_H_
+#define _SOC_PANTHERLAKE_CPU_H_
+
+/* Latency times in us */
+#define C1_LATENCY	1
+#define C6_LATENCY	127
+#define C7_LATENCY	253
+#define C8_LATENCY	260
+#define C9_LATENCY	487
+#define C10_LATENCY	1048
+
+/* Power in units of mW */
+#define C1_POWER	0x3e8
+#define C6_POWER	0x15e
+#define C7_POWER	0xc8
+#define C8_POWER	0xc8
+#define C9_POWER	0xc8
+#define C10_POWER	0xc8
+
+/* Get a bitmask of supported LPM states */
+uint8_t get_supported_lpm_mask(void);
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/crashlog.h b/src/soc/intel/pantherlake/include/soc/crashlog.h
new file mode 100644
index 0000000000..5b988e9729
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/crashlog.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_CRASHLOG_H_
+#define _SOC_PANTHERLAKE_CRASHLOG_H_
+
+#include <types.h>
+
+/* DVSEC capability Registers */
+#define TEL_DVSEC_OFFSET			0x100
+#define TEL_DVSEC_PCIE_CAP_ID			0x0
+#define TEL_DVSEV_ID				0x8
+#define TEL_DVSEV_DISCOVERY_TABLE_OFFSET	0xC
+#define TELEMETRY_EXTENDED_CAP_ID		0x23
+#define CRASHLOG_DVSEC_ID			0x04
+#define TEL_DVSEC_TBIR_BAR0			0
+#define TEL_DVSEC_TBIR_BAR1			1
+
+/* CPU CrashLog MMIO Registers */
+#define CRASHLOG_MAILBOX_INTF_ADDRESS		0x6038
+
+typedef union {
+	struct {
+		u32 reserved1		:27;
+		u32 set_storage_off	:1;
+		u32 set_re_arm		:1;
+		u32 reserved2		:1;
+		u32 set_clr		:1;
+		u32 reserved3		:1;
+	} fields;
+	u32 data;
+} __packed cl_punit_control_interface_t;
+
+#endif /* _SOC_PANTHERLAKE_CRASHLOG_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/dptf.h b/src/soc/intel/pantherlake/include/soc/dptf.h
new file mode 100644
index 0000000000..60b9deb483
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/dptf.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_DPTF_H_
+#define _SOC_PANTHERLAKE_DPTF_H_
+
+/*
+ * Below is a list of unique ACPI Device IDs for thermal and DPTF
+ * (Dynamic Platform and Thermal Framework)
+ */
+/* DPTF ACPI Device ID */
+#define DPTF_DPTF_DEVICE	"INTC10D4"
+/* Generic ACPI Device ID for TSR0/1/2/3 and charger */
+#define DPTF_GEN_DEVICE		"INTC10D5"
+/* Fan ACPI Device ID */
+#define DPTF_FAN_DEVICE		"INTC10D6"
+/* TPCH ACPI Device ID */
+#define DPTF_TPCH_DEVICE	"INTC10D7"
+/* TPWR ACPI Device ID */
+#define DPTF_TPWR_DEVICE	"INTC10D8"
+/* BAT1 ACPI Device ID */
+#define DPTF_BAT1_DEVICE	"INTC10D9"
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h
index 652bed8df0..2ecd28ec84 100644
--- a/src/soc/intel/pantherlake/include/soc/iomap.h
+++ b/src/soc/intel/pantherlake/include/soc/iomap.h
@@ -20,6 +20,9 @@
 #define SAF_BASE_ADDRESS	0x3ffe000000
 #define SAF_BASE_SIZE		0x2000000
 
+/* Add dummy entry to cater common/block/acpi/acpi/northbridge.asl */
+#define DMI_BASE_SIZE		0
+
 #define EP_BASE_ADDRESS		0xfeda1000
 #define EP_BASE_SIZE		0x1000
 
diff --git a/src/soc/intel/pantherlake/include/soc/irq.h b/src/soc/intel/pantherlake/include/soc/irq.h
new file mode 100644
index 0000000000..5d94ed2dbf
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/irq.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_IRQ_H_
+#define _SOC_PANTHERLAKE_IRQ_H_
+
+#define GPIO_IRQ14	14
+#define GPIO_IRQ15	15
+
+#define PCH_IRQ10	10
+#define PCH_IRQ11	11
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/nvs.h b/src/soc/intel/pantherlake/include/soc/nvs.h
new file mode 100644
index 0000000000..c6032f47bc
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/nvs.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_NVS_H_
+#define _SOC_PANTHERLAKE_NVS_H_
+
+#include <intelblocks/nvs.h>
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/p2sb.h b/src/soc/intel/pantherlake/include/soc/p2sb.h
index c431ad6d12..9bf7e2d4b8 100644
--- a/src/soc/intel/pantherlake/include/soc/p2sb.h
+++ b/src/soc/intel/pantherlake/include/soc/p2sb.h
@@ -8,7 +8,7 @@
 
 #define PCH_P2SB_EPMASK0		0x220
 
-extern struct device_operations soc_p2sb_ops;
-extern struct device_operations soc_p2sb_2_ops;
+extern struct device_operations pcd_p2sb_ops;
+extern struct device_operations pcd_p2sb_2_ops;
 
-#endif /* _SOC_PANTHERLAKE_P2SB_H_ */
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/pcie.h b/src/soc/intel/pantherlake/include/soc/pcie.h
new file mode 100644
index 0000000000..89f9c372c4
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/pcie.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_PANTHERLAKE_PCIE_H__
+#define __SOC_PANTHERLAKE_PCIE_H__
+
+#include <intelblocks/pcie_rp.h>
+
+const struct pcie_rp_group *get_pcie_rp_table(void);
+const struct pcie_rp_group *get_tbt_pcie_rp_table(void);
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/pmc.h b/src/soc/intel/pantherlake/include/soc/pmc.h
index daa60f2080..415bf074fb 100644
--- a/src/soc/intel/pantherlake/include/soc/pmc.h
+++ b/src/soc/intel/pantherlake/include/soc/pmc.h
@@ -23,7 +23,7 @@ extern struct device_operations pmc_ops;
 #define   MEM_SR			BIT(21)
 #define   ALLOW_SPXB_CG_INC0		BIT(20)
 #define   ALLOW_L1LOW_C0		BIT(19)
-#define   MS4V				BIT(18)
+#define   MS4V				BIT_FLAG_32(18)
 #define   ALLOW_L1LOW_OPI_ON		BIT(17)
 #define   SUS_PWR_FLR			BIT(16)
 #define   PME_B0_S5_DIS			BIT(15)
diff --git a/src/soc/intel/pantherlake/include/soc/ramstage.h b/src/soc/intel/pantherlake/include/soc/ramstage.h
new file mode 100644
index 0000000000..c906f7d39b
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/ramstage.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_RAMSTAGE_H_
+#define _SOC_PANTHERLAKE_RAMSTAGE_H_
+
+#include <fsp/api.h>
+#include <fsp/util.h>
+#include <soc/soc_chip.h>
+
+void mainboard_silicon_init_params(FSP_S_CONFIG *params);
+void mainboard_update_soc_chip_config(struct soc_intel_pantherlake_config *config);
+void soc_init_pre_device(void *chip_info);
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/serialio.h b/src/soc/intel/pantherlake/include/soc/serialio.h
new file mode 100644
index 0000000000..def55654bf
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/serialio.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_SERIALIO_H_
+#define _SOC_PANTHERLAKE_SERIALIO_H_
+
+enum {
+	PchSerialIoDisabled,
+	PchSerialIoPci,
+	PchSerialIoHidden,
+	PchSerialIoLegacyUart,
+	PchSerialIoSkipInit
+};
+
+enum {
+	PchSerialIoIndexI2C0,
+	PchSerialIoIndexI2C1,
+	PchSerialIoIndexI2C2,
+	PchSerialIoIndexI2C3,
+	PchSerialIoIndexI2C4,
+	PchSerialIoIndexI2C5
+};
+
+enum {
+	PchSerialIoIndexGSPI0,
+	PchSerialIoIndexGSPI1,
+	PchSerialIoIndexGSPI2,
+};
+
+enum {
+	PchSerialIoIndexUART0,
+	PchSerialIoIndexUART1,
+	PchSerialIoIndexUART2
+};
+
+#endif /* _SOC_PANTHERLAKE_SERIALIO_H_ */
diff --git a/src/soc/intel/pantherlake/include/soc/systemagent.h b/src/soc/intel/pantherlake/include/soc/systemagent.h
index c791e5bbe8..fbe8dd25cc 100644
--- a/src/soc/intel/pantherlake/include/soc/systemagent.h
+++ b/src/soc/intel/pantherlake/include/soc/systemagent.h
@@ -15,6 +15,9 @@
 /* MCHBAR offsets */
 #define VTDBAR			0x5410
 #define GFXVTBAR		VTDBAR
+#define  GFXVT_ENABLED		BIT(0)
+#define  NONGFXVT_ENABLED	BIT(1)
+#define  IOCVT_ENABLED		BIT(2)
 #define REGBAR			0x5420
 #define MCH_DDR_POWER_LIMIT_LO	0x58e0
 #define MCH_DDR_POWER_LIMIT_HI	0x58e4
@@ -50,18 +53,6 @@ static const struct sa_mmio_descriptor soc_vtd_resources[] = {
 #define LT_SECURITY_SIZE	(384 * KiB)
 #define APIC_SIZE		(1 * MiB)
 
-#define MASK_PCIEXBAR_LENGTH	0x0000000E // bits [3:1]
-#define PCIEXBAR_LENGTH_LSB	1 // used to shift right
-
-#define  DSM_BASE_ADDR_REG	0xB0
-#define  MASK_DSM_LENGTH	0xFF00 // [15:8]
-#define  MASK_DSM_LENGTH_LSB	8 // used to shift right
-#define  MASK_GSM_LENGTH	0xC0 // [7:6]
-#define  MASK_GSM_LENGTH_LSB	6 // used to shift right
-#define  DPR_REG		0x5C
-#define  MASK_DPR_LENGTH	0xFF0 // [11:4]
-#define  MASK_DPR_LENGTH_LSB	4 // used to shift right
-
 uint64_t get_mmcfg_size(const struct device *dev);
 uint64_t get_dsm_size(const struct device *dev);
 uint64_t get_gsm_size(const struct device *dev);
diff --git a/src/soc/intel/pantherlake/include/soc/tcss.h b/src/soc/intel/pantherlake/include/soc/tcss.h
new file mode 100644
index 0000000000..79604bcfa1
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/tcss.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#ifndef _SOC_PANTHERLAKE_TCSS_H_
+#define _SOC_PANTHERLAKE_TCSS_H_
+
+/* Thunderbolt firmware IMR status */
+#define IOM_CSME_IMR_TBT_STATUS			0x14
+#define TBT_VALID_AUTHENTICATION		BIT(30)
+
+/* IOM aux bias control registers in REGBAR MMIO space */
+#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0	0x1070
+#define IOM_AUX_BIAS_CTRL_PULLUP_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLUP_OFFSET_0 + (x) * 4)
+#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0	0x1088
+#define IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET(x)	(IOM_AUX_BIAS_CTRL_PULLDOWN_OFFSET_0 + (x) * 4)
+
+#define BIAS_CTRL_VW_INDEX_SHIFT 24
+#define BIAS_CTRL_BIT_POS_SHIFT 16
+
+#endif
diff --git a/src/soc/intel/pantherlake/include/soc/usb.h b/src/soc/intel/pantherlake/include/soc/usb.h
new file mode 100644
index 0000000000..1e68d8d73f
--- /dev/null
+++ b/src/soc/intel/pantherlake/include/soc/usb.h
@@ -0,0 +1,155 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef _SOC_PANTHERLAKE_USB_H_
+#define _SOC_PANTHERLAKE_USB_H_
+
+#include <stdint.h>
+
+/* Per Port HS Transmitter Emphasis */
+#define USB2_EMP_OFF			0
+#define USB2_DE_EMP_ON			1
+#define USB2_PRE_EMP_ON			2
+#define USB2_DE_EMP_ON_PRE_EMP_ON	3
+
+/* Per Port Half Bit Pre-emphasis */
+#define USB2_FULL_BIT_PRE_EMP	0
+#define USB2_HALF_BIT_PRE_EMP	1
+
+/* Per Port HS Preemphasis Bias */
+#define USB2_BIAS_0MV		0
+#define USB2_BIAS_11P25MV	1
+#define USB2_BIAS_16P9MV	2
+#define USB2_BIAS_28P15MV	3
+#define USB2_BIAS_39P35MV	5
+#define USB2_BIAS_45MV		6
+#define USB2_BIAS_56P3MV	7
+
+struct usb2_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+	uint8_t tx_bias;
+	uint8_t tx_emp_enable;
+	uint8_t pre_emp_bias;
+	uint8_t pre_emp_bit;
+	uint8_t type_c;
+};
+
+/* USB Overcurrent pins definition */
+enum {
+	OC0 = 0,
+	OC1,
+	OC2,
+	OC3,
+	OC4,
+	OC5,
+	OC6,
+	OC7,
+	OCMAX,
+	OC_SKIP = 0xff, /* Skip OC programming */
+};
+
+/* Standard USB Port based on length:
+ * - External
+ * - Back Panel
+ * - OTG
+ * - M.2
+ * - Internal device down */
+
+#define USB2_PORT_EMPTY { \
+	.enable        = 0, \
+	.ocpin         = OC_SKIP, \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_EMP_OFF, \
+	.pre_emp_bias  = USB2_BIAS_0MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length = 11.5"-12" */
+#define USB2_PORT_LONG(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_39P35MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Length  = 6"-11.49" */
+#define USB2_PORT_MID(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_DE_EMP_ON_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_45MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Length = 3"-5.99" */
+#define USB2_PORT_SHORT(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_39P35MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON | USB2_DE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_39P35MV, \
+	.pre_emp_bit   = USB2_FULL_BIT_PRE_EMP, \
+}
+
+/* Max TX and Pre-emp settings */
+#define USB2_PORT_MAX(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_56P3MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+}
+
+/* Type-C Port, no BC1.2 charge detect module / MUX
+ * Length  = 3.0" - 9.00" */
+#define USB2_PORT_TYPE_C(pin) { \
+	.enable        = 1, \
+	.ocpin         = (pin), \
+	.tx_bias       = USB2_BIAS_0MV, \
+	.tx_emp_enable = USB2_PRE_EMP_ON, \
+	.pre_emp_bias  = USB2_BIAS_56P3MV, \
+	.pre_emp_bit   = USB2_HALF_BIT_PRE_EMP, \
+	.type_c	       = 1, \
+}
+
+struct usb3_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+	uint8_t tx_de_emp;
+	uint8_t tx_downscale_amp;
+};
+
+#define USB3_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+	.tx_de_emp        = 0x00, \
+	.tx_downscale_amp = 0x00, \
+}
+
+#define USB3_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+	.tx_de_emp        = 0x0, \
+	.tx_downscale_amp = 0x00, \
+}
+
+struct tcss_port_config {
+	uint8_t enable;
+	uint8_t ocpin;
+};
+
+#define TCSS_PORT_EMPTY { \
+	.enable           = 0, \
+	.ocpin            = OC_SKIP, \
+}
+
+#define TCSS_PORT_DEFAULT(pin) { \
+	.enable           = 1, \
+	.ocpin            = (pin), \
+}
+
+#endif /* _SOC_PANTHERLAKE_USB_H_ */