diff options
| author | Saurabh Mishra <mishra.saurabh@intel.corp-partner.google.com> | 2024-07-04 19:55:56 +0530 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-11 17:35:27 +0000 |
| commit | de56d38b07b6f17d09286e5e77c0b6cf909ebe08 (patch) | |
| tree | 0b5ed8afcc341e26c015e78b9ef9d70b91b50176 /src/soc/intel/pantherlake/espi.c | |
| parent | 5bc6bd4c41591b9b322436519275dfadd5096474 (diff) | |
soc/intel/ptl: Do initial Panther Lake SoC commit till bootblock
List of changes:
1. Add required Pather Lake SoC programming till bootblock.
2. Include only required headers into include/soc.
3. Include PTL related DID, BDF.
4. Includes additional minimal code required to compile the PTL SoC
and google/fatcat mainbaord.
5. Ref: Processor EDS documents
vol0.51 #815002
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform for
PTL using google/fatcat mainboard.
Change-Id: Ibcfe71eec27cebf04f10ec343a73dd92f1272aca
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83354
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/pantherlake/espi.c')
| -rw-r--r-- | src/soc/intel/pantherlake/espi.c | 47 |
1 files changed, 47 insertions, 0 deletions
diff --git a/src/soc/intel/pantherlake/espi.c b/src/soc/intel/pantherlake/espi.c new file mode 100644 index 0000000000..a3952a31aa --- /dev/null +++ b/src/soc/intel/pantherlake/espi.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/pci.h> +#include <pc80/isa-dma.h> +#include <pc80/i8259.h> +#include <arch/ioapic.h> +#include <intelblocks/itss.h> +#include <intelblocks/lpc_lib.h> +#include <intelblocks/pcr.h> +#include <intelpch/espi.h> +#include <soc/iomap.h> +#include <soc/irq.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/soc_chip.h> + +void soc_get_gen_io_dec_range(uint32_t gen_io_dec[LPC_NUM_GENERIC_IO_RANGES]) +{ + const config_t *config = config_of_soc(); + + gen_io_dec[0] = config->gen1_dec; + gen_io_dec[1] = config->gen2_dec; + gen_io_dec[2] = config->gen3_dec; + gen_io_dec[3] = config->gen4_dec; +} + +void lpc_soc_init(struct device *dev) +{ + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + /* Enable CLKRUN_EN for power gating ESPI */ + lpc_enable_pci_clk_cntl(); + + /* Set ESPI Serial IRQ mode */ + if (CONFIG(SERIRQ_CONTINUOUS_MODE)) + lpc_set_serirq_mode(SERIRQ_CONTINUOUS); + else + lpc_set_serirq_mode(SERIRQ_QUIET); + + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); +} |