soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage

List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 14 insertions, 2 deletions

diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb
index 91e21c09f7..4f6c8e0436 100644
--- a/src/soc/intel/pantherlake/chipset.cb
+++ b/src/soc/intel/pantherlake/chipset.cb
@@ -2,12 +2,24 @@ chip soc/intel/pantherlake
 
 	device cpu_cluster 0 on end
 
-	register "power_limits_config[PTL_U_15W_POWER_LIMITS]" = "{
+	register "power_limits_config[PTL_U_1_CORE]" = "{
 		.tdp_pl1_override = 15,
 		.tdp_pl2_override = 54,
 		.tdp_pl4 = 142,
 	}"
 
+	register "power_limits_config[PTL_H_1_CORE]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 64,
+		.tdp_pl4 = 154,
+	}"
+
+	register "power_limits_config[PTL_H_2_CORE]" = "{
+		.tdp_pl1_override = 25,
+		.tdp_pl2_override = 80,
+		.tdp_pl4 = 240,
+	}"
+
 	# NOTE: if any variant wants to override this value, use the same format
 	# as register "common_soc_config.pch_thermal_trip" = "value", instead of
 	# putting it under register "common_soc_config" in overridetree.cb file.
@@ -116,7 +128,7 @@ chip soc/intel/pantherlake
 				end
 			end
 		end
-		device pci 14.2 alias shared_sram off end
+		device pci 14.2 alias pmc_shared_sram off end
 		device pci 14.3 alias cnvi_wifi off end
 		device pci 14.7 alias cnvi_bluetooth off end
 		device pci 14.5 alias ieh off end