diff options
| author | Jeremy Compostella <jeremy.compostella@intel.com> | 2024-09-20 12:13:11 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-26 03:57:37 +0000 |
| commit | 1005e49580467437cdbe2db8f0c3b6c9b81da357 (patch) | |
| tree | d476c5f6dcbe55679a6de42b1c5ede0319825072 /src/soc/intel/pantherlake/chip.h | |
| parent | 8619d951b3b8b4cb07d5da108421f5dc4a793642 (diff) | |
soc/intel/ptl: Remove tcss_d3_hot_disable en config structure field
This commit drops tcss_d3_hot_disable chip config as FSP is not
exposing the same purpose UPD anymore starting with Panther Lake
SoC.
BUG=b:348678529
TEST=Build for fatcat
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d58
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Diffstat (limited to 'src/soc/intel/pantherlake/chip.h')
| -rw-r--r-- | src/soc/intel/pantherlake/chip.h | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index 9d8bec6ee4..d9028653a6 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -172,8 +172,6 @@ struct soc_intel_pantherlake_config { /* Enable S0iX support */ bool s0ix_enable; - /* Support for TCSS xhci, xdci, TBT PCIe root ports and DMA controllers */ - bool tcss_d3_hot_disable; /* Support for TBT PCIe root ports and DMA controllers with D3Hot->D3Cold */ bool tcss_d3_cold_disable; /* Enable DPTF support */ |