diff options
author | Saurabh Mishra <mishra.saurabh@intel.com> | 2024-09-12 10:52:56 +0530 |
---|---|---|
committer | Subrata Banik <subratabanik@google.com> | 2024-09-13 08:23:55 +0000 |
commit | 95cf9c0052234cf19599c03ea214eff4a6ed3b65 (patch) | |
tree | db9913d476eecffa50466c9df508524119ad29ff /src/soc/intel/pantherlake/Makefile.mk | |
parent | 4ba9eeab08d3ab817b7751dc6f834148667ce065 (diff) |
soc/intel/ptl: Do initial Panther Lake SoC commit till ramstage
List of changes:
1. Add required SoC programming till ramstage.
2. Include only required headers into include/soc.
3. Skeleton code used to call FSP-S API.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: I61930726ad0c765bfa1d72c5df893262be884834
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84332
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/pantherlake/Makefile.mk')
-rw-r--r-- | src/soc/intel/pantherlake/Makefile.mk | 39 |
1 files changed, 37 insertions, 2 deletions
diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk index 2704305026..10ef8e949f 100644 --- a/src/soc/intel/pantherlake/Makefile.mk +++ b/src/soc/intel/pantherlake/Makefile.mk @@ -6,20 +6,55 @@ subdirs-y += romstage subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo +# all (bootblock, verstage, romstage, postcar, ramstage) +all-y += gspi.c +all-y += i2c.c +all-y += pmutil.c +all-y += spi.c +all-y += uart.c +all-y += gpio.c + bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/pcd.c bootblock-y += bootblock/report_platform.c bootblock-y += espi.c -bootblock-y += gpio.c bootblock-y += soc_info.c +romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c -romstage-y += gpio.c romstage-y += meminit.c romstage-y += pcie_rp.c romstage-y += reset.c romstage-y += soc_info.c +ramstage-y += acpi.c +ramstage-y += chip.c +ramstage-y += cpu.c +ramstage-$(CONFIG_SOC_INTEL_CRASHLOG) += crashlog.c +ramstage-y += elog.c +ramstage-y += espi.c +ramstage-y += finalize.c +ramstage-y += fsp_params.c +ramstage-y += lockdown.c +ramstage-y += p2sb.c +ramstage-y += pcie_rp.c +ramstage-y += pmc.c +ramstage-y += reset.c +ramstage-y += retimer.c +ramstage-y += soc_info.c +ramstage-y += soundwire.c +ramstage-y += systemagent.c +ramstage-y += tcss.c +ramstage-y += xhci.c + +smm-y += elog.c +smm-y += gpio.c +smm-y += p2sb.c +smm-y += pmutil.c +smm-y += smihandler.c +smm-y += soc_info.c +smm-y += uart.c +smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/pantherlake CPPFLAGS_common += -I$(src)/soc/intel/pantherlake/include |