soc/intel/ptl: Do initial Panther Lake SoC commit till romstage

List of changes:
1. Add required SoC programming till romstage
2. Include only required headers into include/soc
3. Fill required FSP-M UPD to call FSP-M API
4. Ref: Processor EDS documents
	Panther Lake U/H 12Xe/H 4Xe External Design
	Specification (EDS) Rev. 0.7, vol 1 of 2 #815002 and
	Volume 2 of 2 #813030

BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
     for PTL using google/fatcat mainboard.

Change-Id: I27e1a6c56bca01e7f5f53fbf3cb6855bac7b2848
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83635
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>

1 files changed, 7 insertions, 0 deletions

diff --git a/src/soc/intel/pantherlake/Makefile.mk b/src/soc/intel/pantherlake/Makefile.mk
index 106934a810..477a5d7706 100644
--- a/src/soc/intel/pantherlake/Makefile.mk
+++ b/src/soc/intel/pantherlake/Makefile.mk
@@ -2,6 +2,7 @@
 
 ifeq ($(CONFIG_SOC_INTEL_PANTHERLAKE_BASE),y)
 
+subdirs-y += romstage
 subdirs-y += ../../../cpu/intel/microcode
 subdirs-y += ../../../cpu/intel/turbo
 
@@ -11,6 +12,12 @@ bootblock-y += bootblock/report_platform.c
 bootblock-y += espi.c
 bootblock-y += soc_info.c
 
+romstage-y += espi.c
+romstage-y += meminit.c
+romstage-y += pcie_rp.c
+romstage-y += reset.c
+romstage-y += soc_info.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake
 CPPFLAGS_common += -I$(src)/soc/intel/pantherlake/include