diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.com> | 2024-08-05 15:37:50 -0700 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-09-18 02:17:15 +0000 |
| commit | c43b19ff38c44a4211d314e7d24cceb6cbbf07df (patch) | |
| tree | 50df6c583d723c222a848737534e5acca18a1d0c /src/soc/intel/pantherlake/Kconfig | |
| parent | c512585e55d3ba998c9e2b6ffc6899642e2c297c (diff) | |
soc/intel/ptl: Add SoC ACPI directory for Panther Lake
List of changes:
1. Select common ACPI Kconfig to include common ACPI code block
from IA-common code
2. Select ACPI Kconfig support for wake-up from sleep states.
3. Add SoC ASL code for SoC IPs like IPU, HDA etc.
4. PTL replaces DMI3 with SAF to ensure
common/block/acpi/acpi/northbridge.asl binding with PTL change,
#if DMI_BASE_SIZE guard check is added in northbridge.asl
5. include GPIO ASL that supports new pinctrl schema.
BUG=b:348678529
TEST=Verified on Intel® Simics® Pre Silicon Simulation platform
for PTL using google/fatcat mainboard.
Change-Id: Ia5cf899b049cb8eb27b4ea30c7f3ce7a14884f15
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83772
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/pantherlake/Kconfig')
| -rw-r--r-- | src/soc/intel/pantherlake/Kconfig | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 0dc65e40af..fb6c48bfff 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -14,6 +14,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select DEFAULT_SOFTWARE_CONNECTION_MANAGER if MAINBOARD_HAS_CHROMEOS select DEFAULT_X2APIC_LATE_WORKAROUND select DISPLAY_FSP_VERSION_INFO_2 + select DRIVERS_USB_ACPI select FAST_SPI_SUPPORTS_EXT_BIOS_WINDOW select FSP_COMPRESS_FSP_S_LZ4 select FSP_M_XIP @@ -50,6 +51,13 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BASECODE select SOC_INTEL_COMMON_BASECODE_RAMTOP select SOC_INTEL_COMMON_BLOCK + select SOC_INTEL_COMMON_BLOCK_ACPI + select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC + select SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + select SOC_INTEL_COMMON_BLOCK_ACPI_GPIO + select SOC_INTEL_COMMON_BLOCK_ACPI_LPIT + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP + select SOC_INTEL_COMMON_BLOCK_ACPI_PEP_LPM_REQ select SOC_INTEL_COMMON_BLOCK_CAR select SOC_INTEL_COMMON_BLOCK_CHIP_CONFIG select SOC_INTEL_COMMON_BLOCK_CNVI |