summaryrefslogtreecommitdiff
path: root/src/soc/intel/meteorlake
diff options
context:
space:
mode:
authorSubrata Banik <subratabanik@google.com>2023-04-01 16:27:55 +0530
committerLean Sheng Tan <sheng.tan@9elements.com>2023-04-06 19:32:28 +0000
commit39b7665abe1c5356e0248eddccbd7711ad377ad7 (patch)
treec1ede15552d50f825642193c561264e745d3ec4d /src/soc/intel/meteorlake
parentf5ae1dd1be35daf3012e5773e7ce05f95ffa4da6 (diff)
soc/intel/cmn/cpu: Add function to disable 3-strike CATERR
In Intel designs, internal processor errors, such as a processor instruction retirement watchdog timeout (also known as a 3-strike timeout) will cause a CATERR assertion and can only be recovered from by a system reset. This patch prevents the Three Strike Counter from incrementing (as per Intel EDS doc: 630094), which would help to disable Machine Check Catastrophic error. It will provide more opportunity to collect more useful CPU traces for debugging. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I286037cb00603f5fbc434cd1facc5e906718ba2f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74158 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Diffstat (limited to 'src/soc/intel/meteorlake')
0 files changed, 0 insertions, 0 deletions