diff options
| author | Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> | 2023-07-04 14:58:09 +0530 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2023-07-05 10:36:09 +0000 |
| commit | 6ce1391d1c39a049dd4e834c6f4daaec2de9938d (patch) | |
| tree | 8492a2cc79a3647f5aee28b54cb266b7f96f69d1 /src/soc/intel/meteorlake | |
| parent | 33c6171bdec463112ad24f3c3ac40c1b6fbd5ece (diff) | |
soc/intel/meteorlake: add power limits for 28W SKU
Add power limit values for Meteor Lake 28W SKU.
Reference: Intel MTL-UH_Power_Map_Rev1p2, doc: 640982
BRANCH=None
BUG=b:289854108
TEST=Build FW
Change-Id: I0b4741185278913d11d902d53345ae8ccebb18f8
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/76239
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Diffstat (limited to 'src/soc/intel/meteorlake')
| -rw-r--r-- | src/soc/intel/meteorlake/chipset.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chipset.cb b/src/soc/intel/meteorlake/chipset.cb index b98e4f35b3..1f68eff5e7 100644 --- a/src/soc/intel/meteorlake/chipset.cb +++ b/src/soc/intel/meteorlake/chipset.cb @@ -8,6 +8,12 @@ chip soc/intel/meteorlake .tdp_pl4 = 114, }" + register "power_limits_config[MTL_P_682_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + }" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. |