diff options
| author | Ravi Sarawadi <ravishankar.sarawadi@intel.corp-partner.google.com> | 2022-10-14 12:28:02 -0700 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-11-07 14:22:33 +0000 |
| commit | 640b040f6f204f39a5f710fa019ab9077674826c (patch) | |
| tree | e3b83b8e9dc738b6bbf1406c2d0df7c531df4179 /src/soc/intel/meteorlake | |
| parent | 7d6bf83afcd1263e36ee4b7e7df19790d4417fb0 (diff) | |
soc/intel/meteorlake: Implement SOC Die lock down configuration
This patch implements a function to enable IOSF Primary Trunk Clock
Gating.
BUG=b:253210291
TEST=Able to build and boot rex to OS. Also needed for S0ix, tested
with Sandbox OS + Firmware combination for S0ix entry/exit.
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I02e191336e99f97f4db58b27f4414001b642ad02
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68430
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/soc/intel/meteorlake')
| -rw-r--r-- | src/soc/intel/meteorlake/lockdown.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/lockdown.c b/src/soc/intel/meteorlake/lockdown.c index 678e63a15c..51fbdaf7fa 100644 --- a/src/soc/intel/meteorlake/lockdown.c +++ b/src/soc/intel/meteorlake/lockdown.c @@ -2,10 +2,16 @@ #include <device/mmio.h> #include <intelblocks/cfg.h> +#include <intelblocks/pcr.h> #include <intelpch/lockdown.h> +#include <soc/pcr_ids.h> #include <soc/pm.h> #include <stdint.h> +/* PCR PSTH Control Register */ +#define PCR_PSTH_CTRLREG 0x1d00 +#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -53,8 +59,19 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_smi(); } +static void soc_die_lockdown_cfg(void) +{ + if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + return; + + /* Enable IOSF Primary Trunk Clock Gating */ + pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); +} + void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + /* SOC Die lock down configuration */ + soc_die_lockdown_cfg(); } |