diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2023-01-31 18:49:32 +0530 |
|---|---|---|
| committer | Sridhar Siricilla <sridhar.siricilla@intel.com> | 2023-02-05 17:56:36 +0000 |
| commit | 306bd40939dfee091186d28e1668607bc144decb (patch) | |
| tree | c5c45870debfb1dc48d284894b4eaf7908f6162a /src/soc/intel/meteorlake | |
| parent | 9c471e7defd0897457d7dca290677f1559956afa (diff) | |
mb/intel/mtlrvp: Add chip configuration for I2C devices
This patch adds below chip configuration for I2C devices for mtlrvp.
+-----------+--------------------+-------------+
| INTERFACE | PCI Number (B:D:F) | DEVICE |
+-----------+--------------------+-------------+
| I2C0 | 0:0x15:0 | CAM1 |
+-----------+--------------------+-------------+
| I2C1 | 0:0x15:1 | CAM0 |
+-----------+--------------------+-------------+
| I2C2 | 0:0x15:2 | NC |
+-----------+--------------------+-------------+
| I2C3 | 0:0x15:3 | HID |
+-----------+--------------------+-------------+
| I2C4 | 0:0x15:4 | NC |
+-----------+--------------------+-------------+
| I2C5 | 0:0x15:5 | NC |
+-----------+--------------------+-------------+
BUG=b:224325352
BRANCH=None
TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus
enumeration through lspci.
00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01)
00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01)
00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia5964472be902041f961187c0072a89055badd4f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Diffstat (limited to 'src/soc/intel/meteorlake')
0 files changed, 0 insertions, 0 deletions