soc/intel/*: drop broken LPC mmio code

The code for setting the LPC generic memory range uses an array of fixed
address ranges not needing explicit decoding, to decide if the address
needs to be written to the LGMR register. Most platforms only mistakenly
add the PCH reserved mmio range, that is not decoded generally,
effectively breaking the mechanism. Only APL uses the array correctly.

That code, in it's current state, does not work (except for APL) and
currently, there is not a single user. Thus, drop it before people start
using it.

Change-Id: I723415fedd1b1d95c502badf7b0510a1338b11ac
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

1 files changed, 0 insertions, 15 deletions

diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c
index 11299a9552..3911c81c3d 100644
--- a/src/soc/intel/jasperlake/espi.c
+++ b/src/soc/intel/jasperlake/espi.c
@@ -17,21 +17,6 @@
 #include <soc/pcr_ids.h>
 #include <soc/soc_chip.h>
 
-/*
-* As per the BWG, Chapter 5.9.1. "PCH BIOS component will reserve
-* certain memory range as reserved range for BIOS usage.
-* For this SOC, the range will be from 0FC800000h till FE7FFFFFh"
-*/
-static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = {
-	{ PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE },
-	{ 0, 0 }
-};
-
-const struct lpc_mmio_range *soc_get_fixed_mmio_ranges()
-{
-	return jsl_lpc_fixed_mmio_ranges;
-}
-
 void soc_get_gen_io_dec_range(uint32_t *gen_io_dec)
 {
 	const config_t *config = config_of_soc();